Integrated Circuit Design Verification Engineer

Responsibilities

• Work as part of a multi-disciplinary team designing display Integrated Circuits for AR
• Work closely with digital design, analog logic, software and verification engineers
• Develop and implement UVM-based and assertion-based test benches
• Create and execute verification test plans, including functional coverage and code coverage
• Utilize Siemens Questa tool set for verification and debug tasks
• Specify and configure tools and create automation

• BSEE or MSEE or relevant years of experience
• 10+ years of experience in ASIC Design Verification
• Strong knowledge of UVM and System Verilog for advanced verification methodologies
• Strong knowledge of digital functional simulation, and tools such as Siemens Questa
• Strong knowledge of good Verilog RTL coding practices
• Scripting and automation, such as TCL, Make, Perl, Python and Shell scripts in Linux environment
• Ideal candidate is a self-starter, can organise complex issues and drive them to closure
• Able to multitask and prioritise.