Senior Digital Hardware Engineer — FPGA & Signal Integrity

Application close date:
Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we are developing reusable space vehicles and systems within a culture of safety, collaboration, and inclusion. As a Senior Digital Hardware Engineer, you will design and develop FPGA‑based hardware for our next‑generation RF communication and beamforming systems.

• Design FPGA‑based digital boards that interface with beamforming ASIC carrier boards, providing high‑speed control interfaces and precision clock distribution.
• Design digital interface and timing distribution boards that connect back‑end processing to phased array antenna modules.
• Design mixed‑signal payload integration assemblies that manage power, clocking, and inter‑board data routing.
• Create complete electrical schematics in Altium Designer for FPGA‑based boards, including I/O bank planning, power rail grouping, configuration circuitry, and JTAG/debug infrastructure.
• Design multi‑rail power distribution for FPGAs and ASICs, including sequencing, point‑of‑load regulators, and power monitoring.
• Select and evaluate components with consideration for performance, availability, and temperature range.
• Define PCB stackup requirements in collaboration with fabrication partners, specifying laminate selection, copper weights, and layer assignments for impedance and loss targets.
• Author routing constraint documents for high‑speed interfaces (JESD
  204B/C, DDR4, LVDS), covering length matching, topology, spacing, termination, and reference plane rules.
• Perform pre‑ and post‑layout SI review using simulation tools (Hyper Lynx, SIwave, or equivalent), focusing on via stub effects, crosstalk, and connector transitions.
• Review third‑party layout deliverables against constraint documents and SI simulation results, providing clear and actionable feedback.
• Support PDN analysis for FPGA and ASIC power rails.
• Develop board bring‑up procedures and test plans for first‑article fabrication.
• Support hardware bring‑up using oscilloscopes, logic analyzers, and BERT instruments to characterize high‑speed interfaces.
• Debug and document hardware issues, driving root‑cause analysis and design corrections.

• B.S. in Electrical Engineering or a related field with 5+ years of board‑level hardware design experience.
• Hands‑on schematic design experience with high‑performance FPGAs (Xilinx Ultra Scale+, Intel Agilex, or equivalent).
• Working knowledge of signal integrity fundamentals: transmission lines, impedance control, via effects, and termination—sufficient to author layout constraints and review third‑party layouts.
• Experience designing and validating high‑speed serial interfaces at 16
  
  Gbps lane rates or higher, with direct ownership of schematic and SI analysis at that rate.
• Experience with at least one high‑speed serial interface standard (JESD
  204B/C, PCIe Gen4/5, or equivalent) including schematic ownership.
• Proficiency in Altium Designer for multi‑sheet schematic design.
• Familiarity with SI simulation tools (Hyper Lynx, SIwave, or equivalent) at a layout review level.
• Hands‑on bring‑up experience with oscilloscopes, logic analyzers, and standard lab equipment.

• Experience designing hardware for phased array or beamforming systems, including phase array antenna module interfaces, array timing distribution, or beamforming ASIC integration.
• Familiarity with JESD
  204B/C deterministic latency, SYSREF distribution, and multi‑converter synchronization.
• Familiarity or hands‑on experience with Precision Time Protocol (PTP / IEEE
  1588) or VITA
  49.2 (VRT) in hardware implementations, including hardware time stamping, PTP‑aware switch and PHY selection, clock recovery circuit design, or FPGA‑based VITA
  49.2 packetization and timing metadata.
• Experience with mixed‑signal or RF/digital PCB design.
• Exposure to space, aerospace, or high‑reliability hardware design environments.
• Experience working with and technically directing third‑party PCB design or EMS partners.
• Experience analyzing and mitigating EMI/EMC challenges inherent to mixed‑signal boards combining GHz‑rate digital signals with sensitive analog and RF circuitry.