PLL Design Engineer
Job in
Irvine, Estill County, Kentucky, 40336, USA
Listed on 2026-06-02
Listing for:
Celero Communications, Inc.
Full Time
position Listed on 2026-06-02
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Electrical Engineering, Hardware Engineer
Job Description & How to Apply Below
About the job
Are you a PLL Design Engineer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI? We are looking for a High-Speed CMOS PLL Analog Design Engineer -who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers, high-speed Ser Des, and ADC/DAC systems
Preferred Location - On-Site at one of our offices:
San Jose, CA, or Irvine, CA HQ
Alternate Locations - Vancouver, British Columbia;
Ottawa, Ontario
Candidate will have the opportunity to architect and design PLLs for next generation transceivers.
What You Will Do:
- Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range
- Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre
- Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization
- Supervise and verify layouts produced by layout engineers to ensure floor planning, matching, and parasitic minimization using advanced node technologies
- Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment
- Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies
- Master's degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience.
- Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
- Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs
- Proficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling
- Strong communication and documentation skills
$150,000 - $250,000 Annually
The final offer will be determined based on job-related skills, experience, qualifications, and location.
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
Search for further Jobs Here:
×