Digital Design Lead

AIDAChip is the Alignment OS for AI-native silicon engineering teams — the first AI platform built for chip design teams, not just individuals. Chip design today is fragmented across disciplines, tools, and handoffs, so intent gets lost and work drifts. We're the shared nervous system that keeps intent, knowledge, and execution aligned from specification to tapeout.

We build a multiplayer system, not a shelf of standalone agents: our AI teammates share design intent, compound what the team learns, and run EDA flows.
The alignment is the product; the agents and the platform are how it gets delivered.

You are the human authority on digital design for that system. You decide what "correct" means for each digital AI teammate, when it's good enough to put in front of a customer, and how they behave as a set rather than as point tools. Everything you shape ships to someone with a tapeout date, and the AI does not do the engineering for you.

You are the reason it gets good.

• Every digital AI teammate on the platform — Architecture, RTL, DV, synthesis and place-and-route agents, signoff checkers, and the handoffs between them. You set what "correct" means for each, the bar for putting it in front of a customer, and how they behave as a system rather than point tools.
• Customer playbooks — turn a customer's methodology, constraint style, signoff bar, and waivers into something repeatable we can deploy. This is customer-facing work. (You’ll partner with our forward-deployed engineers, who own the deployment relationship — you own the digital methodology depth.)
• The mixed-signal seam — AMS flows and mixed-signal IP: real-number modeling, digital-to-analog interface verification, top-level integration.

• 10+ years in digital IC design, with deep hands‑on depth in at least two of design, functional verification, and physical implementation — and credible in the third. The breadth is the job, not a bonus.
• Multiple tapeouts owned end to end, with silicon in production — some at advanced nodes.
• Synthesis, place-and-route, and signoff fluency across industry flows (Synopsys, Cadence, Siemens). Static timing analysis, clock/reset-domain crossing, UPF.
• DFT: scan insertion, ATPG, MBIST, boundary scan.
• Verification:
  System Verilog and UVM, coverage closure, and a considered opinion about where formal earns its keep and where it doesn’t.
• Flow engineering in TCL and Python. You’ve built and maintained a flow other engineers depended on — and you were the one paged when it broke.
• Writing clear enough to specify behavior for a system that follows your words literally. This matters more here than in a normal design role.

• Mixed-signal exposure: AMS simulation, real-number modeling in System Verilog, analog-digital interface verification.
• Hands-on time with LLMs or agentic tooling — even if it went badly. We’d rather hear what failed.
• CAD and automation background.

• Evidence over vibes: nothing is "done" until it’s proven — results carry their proof, claims are verified before they’re asserted, and failures surface loudly instead of slipping through
• Measured, not narrated: if it isn’t measured, it didn’t happen — we decide on data in a shared system of record, not on how good the update sounded
• Agent leverage: every person directs a fleet of AI teammates and delivers at a multiple of what a lone expert could, without lowering the bar
• Human-in-the-loop by design: the AI proposes; a human owns the calls that matter — judgment stays with the expert
• Greenfield ownership: you own a whole problem end to end — a real workstream on a production platform serving enterprise silicon customers, not a demo