Design Test Lead

About Neurophos

The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape the future of computing!

Location: Austin, TX or Sunnyvale, CA. Full-time onsite position.

Reports To
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FLSA Status
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Exempt

We're hiring a DFT Architect to own design-for-test for our electronic IC. You'll set the DFT strategy for the full chip, own coverage assessment and signoff, and work with the RTL and physical design teams to build testability in from the start. This is our first dedicated DFT hire, so you'll define how test gets done here and grow the team that executes it, working directly with the analog team on their test requirements and owning the handoff into the post-silicon test program.

• Own DFT architecture and test control design for multiple ASIC devices using ATPG

  scan (stuck-at/at-speed), MBIST, and boundary scan / JTAG. Architecture to include

  MCM and external HBM memory module DFT capabilities as well.

• Architect on-die memory test, including controller specification and generation, pattern

  selection, RAM grouping and system test time and power analysis.

• Work with operations and PE teams to ensure all test modes are fully implemented,

  including HAST and other product qualification functions.

• Architect system level wafer and package level DFT plans for all phases of the product

  development process.

• Create and deploy integrated DFT development flow with critical metrics allowing quick

  analysis and updates to achieve near 100% test coverage.

• Own coverage assessment and signoff, including where to accept a coverage gap and

  the reasoning behind it.

• Develop and specify functional test vectors to augment structural coverage.

• Specify analog test requirements to the analog team, including self-test and loopback

  approaches.

• Build testability into RTL and implementation early, partnering with the RTL and physical

  design teams.

• Own handoff to the post-silicon test program, working with operations and package

  teams on where system-level validation picks up.

• Own delivery and deployment of production level test plan to OSAT

• 8 to 15 years in DFT, with hands-on ownership of scan, ATPG, and MBIST.

• Architect-level experience on a large digital ASIC: you've assessed a full chip, set the

  DFT strategy, and owned coverage signoff.

• Experience developing and specifying functional test vectors to augment structural

  coverage.

• Track record through tapeout on a complex compute ASIC.

• Analog test specification experience: defining what it takes to test analog circuits and

  working that out directly with the analog team.

• Cadence toolchain experience

• Exposure to silicon…