Senior Mixed-Signal Post-Silicon Validation Engineer Seattle, WA

Senior Mixed-Signal Post-Silicon Validation Engineer

Seattle, WA

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches in 2027 and plans to scale to 100 satellites a year, we’re Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you’re excited about contributing to the success of a high-growth Series D-funded company, we’d love for you to apply.

We are looking for a hands‑on Senior Mixed‑Signal Post‑Silicon Validation Engineer to bring up and characterize complex mixed‑signal SoCs from first silicon through product integration.
You will work closely with analog/mixed‑signal designers, systems/DSP, firmware, FPGA, digital, and hardware teams to validate silicon performance, debug issues, and build our test and validation capability from the ground up.

• Bring up and characterize mixed‑signal silicon, including ADCs, DACs, PLLs, clocking, references, power, and analog signal paths.
• Develop and execute characterization plans across frequency, voltage, temperature, process, and operating modes.
• Measure key converter and analog performance including SNDR, SFDR, ENOB, INL/DNL, noise, bandwidth, jitter, phase noise, linearity, and power.
• Develop automated test setups for characterization, regression, data collection, analysis, and reporting.
• Work closely with analog/mixed‑signal designers to correlate silicon measurements with simulations and identify performance gaps.
• Partner with systems/DSP teams to validate DSP and calibration algorithms on silicon and correlate results with system models.
• Debug complex issues spanning silicon, firmware, package, PCB, test setup, and system behavior.
• Support the transition from chip‑level validation to product integration and system‑level testing.
• Contribute to building the validation lab, test infrastructure, measurement methodology, and automation from the ground up.
• Document characterization results, silicon limitations, workarounds, and lessons learned for future silicon generations.

• BS/MS in Electrical Engineering or related field.
• 5+ years of mixed‑signal silicon validation, characterization, product engineering, or related experience.
• Strong understanding of ADC, DAC, PLL, clocking, and analog circuit fundamentals.
• Deep hands‑on experience with lab test equipment such as high‑speed oscilloscopes, spectrum/signal analyzers, vector signal generators, phase‑noise analyzers, network analyzers, power supplies, and related mixed‑signal instrumentation.
• Experience developing automated characterization environments using Python or similar scripting languages and instrument‑control interfaces.
• Strong understanding of signal integrity, noise, clock jitter, spectral analysis, and mixed‑signal…