ASIC Engineer, Power Management Design Verification

# ASIC Engineer, Power Management Design Verification Sunnyvale, CA+1 location

Engineering+ 3 more Apply nowMeta's Infrastructure Silicon team is seeking a Staff ASIC Design Verification Engineer to lead verification strategy and execution for custom silicon powering Meta's data center infrastructure. In this role, you will architect and drive end-to-end verification of complex IP blocks and SoCs designed for AI/ML acceleration, networking, and storage workloads. You will define scalable UVM-based verification environments, establish coverage closure methodologies, and partner with design, emulation, and post-silicon validation teams to ensure first-pass silicon success across Meta's infrastructure ASIC portfolio.

---## ASIC Engineer, Power Management Design Verification Responsibilities
* Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
* Develop functional tests based on the verification test plan
* Drive design verification to closure based on defined verification metrics on the test plan, functional, and code coverage
* Debug, root-cause and resolve functional failures in the design, partnering with the design team
* Collaborate with cross-functional teams like Design, Model, Emulation, and silicon validation teams towards ensuring the highest design quality
* Develop and drive continuous design verification improvements using the latest verification methodologies, tools, and technologies from the industry##

Minimum Qualifications
* Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience