ASIC Physical Design Engineer

We’re hiring for a full-time opportunity with a leading semiconductor end client in Lafayette, IN. Seeking experienced ASIC Physical Design / Backend Engineers with strong TSMC FinFET tapeout and signoff experience.. Detailed job description is given below.
Title: ASIC Physical Design Engineer (TSMC / FinFET)
Location:
Lafayette, Indiana (“Relocation assistance provided”)
Type:
Full time with Client

• Tapeout , Signoff , DRC/LVS/PEX, Customer interaction

• Act as the primary interface between customers and semiconductor foundries to ensure successful tape-outs
• Guide customers through design sign-off, including sharing required documentation and technical requirements
• Collaborate with internal design, layout, and engineering teams to ensure manufacturability
• Prepare, review, and validate designs for fabrication using EDA tools
• Support customer engagements by providing technical expertise during pre-sales and project execution
• Partner with customers throughout the chip design and manufacturing lifecycle to ensure a smooth experience
• Coordinate with foundry partners (primarily TSMC) on specifications, timelines, and fabrication requirements
• Track project milestones and drive on-time delivery
  
  Maintain accurate documentation of project status, customer communication, and technical details
• Identify and implement process improvements and automation opportunities

• Proven tape-out experience with advanced TSMC nodes (e.g., FinFET technologies)
• Strong understanding of semiconductor backend processes
• Experience working directly with customers and external partners
• Excellent communication skills (written and verbal)
• Ability to manage multiple priorities and solve complex technical issues
• Proactive, detail-oriented, and team-oriented mindset
• Familiarity with Linux environments
• Basic scripting or programming experience