FPGA Design​/Verification Engineer Security Clearance

Position: FPGA Design/Verification Engineer with Security Clearance
Position: FPGA Design Engineer

Location:

Littleton, CO
Rolling Contract
Secret Clearance Required The selected candidate will be responsible for ASIC & FPGA verification utilizing UVM. Key activities you will accomplish in this role:
• Support other aspects of ASIC and FPGA development such as architecture, design, analysis, and test.

• Support technical reviews and be able to present to internal and external customers

• Devise a unique verification plan for a given design.

• Use System Verilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment.

• Document verification plan and results.

• Work with an independent verification team to resolve bugs found in the design. To be effective in this role, you will need:
• ASIC/FPGA verification experience with modern verification methodologies such as UVM, OVM or VMM.

• 3+ years professional experience.

• Active DoD Secret clearance