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Formal Verification Engineer: ASIC/FPGA; SVA
Job in
Livermore, Alameda County, California, 94551, USA
Listed on 2026-07-04
Listing for:
Sandia National Laboratories
Full Time
position Listed on 2026-07-04
Job specializations:
-
Engineering
Test Engineer, Electronics Engineer
Job Description & How to Apply Below
Sandia National Laboratories is seeking a Digital Verification Engineer (R&D Electrical Engineer) to ensure correct functionality of ASIC and FPGA designs. The candidate should have expertise in VHDL, Verilog, and System Verilog Assertions and be detail-oriented.
This position offers a hybrid work model with remote flexibility from any U.S. state, requiring occasional travel to California.
Competence in formal verification and strong communication skills are essential, alongside a Bachelor’s degree in a relevant field.
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