FPGA Design Engineer

Long Wall Company was created in 2024 to accelerate missile defense technology for the U.S. and our allies. Building on the RS1 and GS0 launch systems, Long Wall develops containerized, mass‑producible missile defense systems and offers rapid, low‑cost flight testing. We believe that the future of global security and stability requires defensive technology that is lower cost, higher performing, better tested, and more broadly distributed than is possible today.

As a Firmware/FPGA Engineer, you will lead the design, development, and integration of FPGA‑based embedded systems at Long Wall to support our launch operations and test infrastructure. You will be a key member of a small team of hardware, software, and systems engineers working to develop innovative high‑performance data acquisition and processing solutions that enable the rapid deployment of Long Wall launch and test systems.

Your responsibilities will include FPGA firmware development from concept to production, custom IP core design, high‑speed interface implementation, hardware/software integration, and test stand FPGA development, ensuring alignment with strategic business goals.

• Design, implement, and verify FPGA firmware for Xilinx and AMD‐based systems, including SoC and ACAP architectures.
• Debug and validate firmware through hardware‑in‑the‑loop testing and system integration.
• Collaborate with hardware engineers to define FPGA I/O requirements and board‑level interfaces.
• Collaborate with software engineers to design CPU driver interfaces for custom IP cores.
• Create and maintain technical documentation, including design specifications, timing reports, and test plans.
• Contribute to architecture decisions for FPGA/embedded systems and participate in design reviews.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of hands‑on FPGA development experience with AMD/Xilinx platforms.
• Expert‑level knowledge of Xilinx FPGA architectures and Zynq SoC platforms.
• Strong understanding of digital design principles, timing analysis, and clock domain crossing techniques.
• Experience with Xilinx Vivado design suite for synthesis, implementation, and debugging.
• Demonstrated ability to bring FPGA designs from concept through production.
• Extensive experience with troubleshooting designs and resolving integration issues.
• Excellent communication and presentation skills.
• Proficiency in HDL languages (VHDL and/or Verilog/System Verilog).
• Proven experience with Vivado and Vitis tool chains, including IP integration, timing constraints, and build automation.
• Experience developing custom IP cores with register interfaces, interrupt generation, and DMA engine integration.
• Understanding of high‑speed serial interfaces (Ser Des) and multi‑gigabit transceiver architectures.
• Strong knowledge of streaming video/data architectures, including buffering strategies, flow control, and memory management.
• Implementation of high‑speed communication protocols: PCIe (Gen 1/2/3/4/5), 1G/10G/25G Ethernet MAC/PHY layers (SGMII, RGMII, UXSGMII).
• Design and optimization of streaming DMA architectures and high‑throughput data paths.
• Multi‑clock domain design, including proper CDC techniques and metastability mitigation.
• Ability to collaborate with software engineers on hardware/software interfaces, including memory‑mapped register design and interrupt architecture.
• Strong debugging skills using Vivado ILA, VIO, and hardware test equipment (oscilloscopes, logic analyzers).
• Proficiency with version control systems (Git) and CI/CD workflows for FPGA development.
• Master's degree in electrical engineering, computer engineering, or related field (preferred).
• Experience with Versal ACAP systems and Network‑on‑Chip (NoC) design requirements and profiling.
• Experience with Xilinx High‑Level Synthesis (HLS) for algorithm acceleration.
• Experience with Versal AI Engine development and optimization.
• Knowledge of AXI/AXI‑Stream protocols and custom IP core development.
• Experience with video processing pipelines, frame buffering, and line buffering architectures.
• Understanding of driver development concepts and register‑level…