Computer Aided Design Engineer

Compensation:

Base Salary $250K - $350K + Competitive Equity

• The client uses AI to optimize power, performance, and area in physical chip design — solving problems humans literally can't solve alone. They're the only startup tackling PPA optimization in physical design with this approach.
• Founded by a former Google exec (led 600-person teams) and a world-renowned UT Austin professor with 500 research papers. $6M pre-seed closed in March with another round coming in September. Already partnered with Global Foundries and working with top semiconductor companies.
• EDA/CAD Engineer role with $250k–$350k salary + 0.01–1.5% equity. Hybrid in Los Altos (Mon–Thu on-site). Hiring 3–7 engineers — ground-floor opportunity at a company with 5 people today.

• 2 - 7 years of experience in VLSI physical design or EDA tool development
• Experience building EDA tools (not just running scripts)
• Algorithmic/optimization skills (not just scripting)
• Wants to build tools, not just use them
• BS/MS/PhD in EE, Computer Engineering, or CS

• Hands- on place & route or physical design R&D
• Proficiency with industry- standard EDA tools and flows
• Experience at advanced process nodes (7nm and below)
• Degree from a strong engineering program

• Worked at Synopsys, Cadence, Intel, Nvidia, or similar

• 20+ years at one big company (likely too rigid)
• Only frontend/RTL experience with no backend exposure
• Pure script- runner with no interest in algorithms/optimization

We are looking for an EDA/CAD Engineer with 2-7 years of experience to join the client and help build AI-powered tools that optimize power, performance, and area in semiconductor physical design. You'll be joining a founding team led by world-renowned experts in EDA and VLSI CAD who are tackling the hardest problems in chip design at a seminal moment — Moore's Law is ending, and AI offers a once-in-a-generation opportunity to transform the industry.

This is a high-ownership role where you'll work directly with major semiconductor customers (including Global Foundries) and have a meaningful impact from day one. We need someone who deeply understands how chips are built and is passionate about writing tools to optimize the design process.

• Implementing complex design rules from major foundries into the client's AI-powered physical design optimization system
• Building EDA software tools focused on place and route, PPA optimization, and backend IC implementation
• Working directly with top-tier semiconductor customers every week, owning large pieces of customer-facing deliverables
• Contributing to both tactical feature development (closing gaps, fixing bugs, shipping features) and strategic projects (agentic flows, pre-trained model integration)
• Collaborating with a small, elite team of PhDs and engineers to push the boundaries of what's possible in AI-driven chip design

Cadence, Synopsys, Python, Tcl, Perl, Place and Route Tools, Physical Design Tools, DRC