Senior ASIC Physical Design Engineer

About K2 Space: K2 is a space startup building the largest and highest power satellites ever flown.

Senior ASIC Physical Design Engineer – responsible for implementing advanced SoCs that power next generation satellite and space systems. Work through the full physical design flow—from synthesis to GDSII—collaborating with architecture, RTL, verification, and packaging teams to achieve timing closure, optimize PPA, and support design integration with external partners.

• Execute the complete physical design flow for complex SoC blocks and top level integration, including synthesis, floor planning, place & route, CTS, STA, and physical verification.
• Perform timing closure and optimization across multiple corners and modes using industry standard tools.
• Collaborate with front end, verification, and DFT teams to ensure clean handoff and predictable convergence.
• Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment.
• Develop and maintain scripts and automation to improve flow efficiency and consistency.
• Support physical sign off activities including DRC/LVS, IR drop, EM, and power analysis.
• Assist in chip level integration, ECOs, and tapeout preparation.
• Contribute to methodology development, tool evaluation, and flow documentation.
• Support the product through production and spaceflight.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5-10 years of experience in ASIC physical design for complex SoCs.
• Hands on experience with industry standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
• Strong understanding of timing analysis, power optimization, and physical verification flows.
• Experience with hierarchical or flat SoC design methodologies.
• Familiarity with FinFET technologies.
• Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
• Strong problem solving skills and ability to work cross functionally in fast paced environments.

• Exposure to radiation hardened or space qualified ASICs.
• Experience with chip package co design or advanced packaging (2.5D/3D).
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience with sign off through TSMC.
• Experience with Gate All Around technologies.
• Experience working in cross functional, geographically distributed teams.

• Base salary range: $170,000 – $250,000 + equity in the company.
• Compensation determined by knowledge and skills, education, and experience level.
• Comprehensive benefits: paid time off, medical dental vision coverage, life insurance, paid parental leave, and other perks.

As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). The role requires access to information and items controlled by U.S. export control regulations and the individual must be an eligible U.S. person as defined by 22 C.F.R. 120.15. If not eligible, a federal export control license is required.

K2 Space is an Equal Opportunity Employer; employment is governed on merit, competence, and qualifications and will not be influenced by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, or any other legally protected status. If you need a reasonable accommodation during the application or interview process, please let us know.