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Principal Engineer Digital FPGA​/Sr. Principal Engineer Digital FPGA; Level 3​/R10220062

Job in Manhattan Beach, Los Angeles County, California, 90266, USA
Listing for: Northrop Grumman
Full Time position
Listed on 2026-02-16
Job specializations:
  • Engineering
    Systems Engineer, Electrical Engineering
Salary/Wage Range or Industry Benchmark: 100000 - 125000 USD Yearly USD 100000.00 125000.00 YEAR
Job Description & How to Apply Below
Position: Principal Engineer Digital FPGA/Sr. Principal Engineer Digital FPGA (Level 3/4) - R10220062

Overview

RELOCATION ASSISTANCE:
Relocation assistance may be available. CLEARANCE TYPE: SCI. TRAVEL:
Yes, 10% of the Time.

Description

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people’s lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history — from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon.

We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they’re making history.

Strategic Space Systems Division (SSSD) is an industry-leading provider for prime satellite and payload capabilities and directed energy and electronics solutions for national security, military, and civil customers. We are built on a heritage of providing innovative, affordable and reliable aerospace and defense products that our customers rely on to achieve mission success. Join the Space revolution and make the impossible, possible.

The Ground Systems Development Department (part of Northrop Grumman Space Systems Sector) in Manhattan Beach, CA is seeking a talented Principal Engineer Digital FPGA/Sr. Principal Engineer Digital FPGA (Level 3/4) to join our team in the development and integration of complex electronic test systems and electronic hardware units in support of space flight programs. This individual would act as a responsible design engineer (RDE) supporting digital development on our program.

The RDE responsibilities include FPGA and PCB: architecture design, detailed design, performing customer briefings/reviews, and hardware test. Primary deliverables are flight electronics test systems and satellite system operational ground-based hardware.

The candidate will perform designs in a team environment with other engineering functions, including Ground Hardware Engineering, Flight Hardware Engineering, Systems Engineering, Product Engineering, Software Engineering, Production, Procurement, and Program Management to meet schedule and technical requirements.

Responsibilities
  • Design, integration, and test of Digital circuits
  • FPGA development
  • PCBs/CCA design
  • Electronic drawer/unit design
  • Small to large electronic subsystems
Some Responsibilities Include Performing The Following
  • Detailed Digital analysis at the component level
  • FPGA design, functional simulation, and test vector creation
  • PCB/CCA design, development, test, and integration
  • Electronic Unit design, development, test, and integration
  • Electronic Test System (Test Set) design, development, test, and post-delivery support
  • Worst case performance analysis for critical Digital signals
  • Developing and presenting design reviews for internal and external customers
Benefits
  • Medical, Dental & Vision coverage
  • 401k
  • Educational Assistance
  • Life Insurance
  • Employee Assistance Programs & Work/Life Solutions
  • Paid Time Off
  • Health & Wellness Resources
  • Employee Discounts

This position’s standard work schedule is a 9/80. The 9/80 schedule allows employees who work a nine-hour day Monday through Thursday to take every other Friday off.

This position can be filled at level 3 or 4.

Basic Qualifications Level 3 – Principal Engineer Digital FPGA
  • Bachelor’s degree in Electrical or Computer Engineering, or another STEM degree from an accredited institution and 5+ years of engineering experience; OR 3+ years of engineering experience with a STEM Master’s degree; OR 0+ years of experience with a STEM PhD.
  • Must have active SCI clearance (Required Day
    1).
Level 4 – Sr. Principal Engineer Digital FPGA
  • Bachelor’s degree in Electrical or Computer Engineering, or another STEM degree from an accredited institution and 9+ years of engineering experience; OR 7+ years with a STEM Master’s degree; OR 4+ years with a STEM PhD.
  • Design and test experience in electronics or digital technology
  • Previ…
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