Principal Electrical Engineer-FPGA Verification

Location: US-MA-TEWKSBURY, 50 Apple Hill Dr, ASSABET BLDG

Position Role Type: Onsite

U.S. Citizenship / Security Clearance: U.S. citizenship required. Ability to obtain/maintain a U.S. government‑issued security clearance required. DoD Clearance:
Secret. Active and existing security clearance required after day 1.

• Own or contribute to the successful completion of FPGA-based designs, on time and on budget.
• Verify designs utilizing self‑checking techniques with directed and constrained random tests, while tracking functional and code coverage using UVM.
• Create complete documentation including verification plan and report.
• Demonstrate self‑motivation with little supervision required.
• Work cooperatively with systems, hardware, software engineers, and program management to ensure product success.
• Support internal and external technical reviews.

• Degree in STEM and a minimum of 8 years of prior relevant experience.
• Digital design verification experience.
• Strong proficiency in System Verilog for both design and verification (interfaces, clocking blocks, assertions).
• Hands‑on experience building UVM‑based test benches from scratch, including env, agent, scoreboard, and coverage components.
• Solid understanding of constrained‑random verification and functional coverage methodology.
• Familiarity with AXI, PCIe, Ethernet, DDR protocols.
• Experience with industry‑standard simulators (e.g., Questa, VCS, Xcelium).
• Experience with regression management and debugging of complex, intermittent failures.
• Ability to develop and maintain verification plans tied to design specifications and coverage closure criteria.
• Experience with version control systems (e.g., Git, Clear Case, SVN) in a team‑based development environment.

• Proficiency with Git, branching strategies, pull requests, and collaborative workflows.
• Experience with UVMF (UVM Framework) for structured, reusable testbench development.
• Familiarity with Vivado and Quartus FPGA simulation flows.
• Experience with scripting languages (Python, Tcl, Perl) for test automation and tooling.
• Experience designing FPGAs using VHDL.
• Familiarity with SLURM workload manager for job scheduling and compute cluster resource management.
• Prior experience mentoring junior verification engineers.
• Existing DoD security clearance.

Values driving our actions, behaviours, and performance with a vision for a safer, more connected world. At RTX we value:
Safety, Trust, Respect, Accountability, Collaboration and Innovation. This position is eligible for relocation.

Salary range: 107,500 USD – 204,500 USD. Potential benefits include medical, dental, vision, life insurance, short‑term disability, long‑term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays.

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status, or any other applicable state or federal protected class. RTX provides affirmative action in employment for qualified individuals with a disability and protected veterans in compliance with Section 503 of the Rehabilitation Act and the Vietnam Era Veterans’ Readjustment Assistance Act.