Principal Electrical Engineer - FPGA Verification

Location

US-MA-TEWKSBURY-TB1 ~ 50 Apple Hill Dr ~ ASSABET BLDG

United States of America

US-MA-TEWKSBURY-TB1 ~ 50 Apple Hill Dr ~ ASSABET BLDG

Onsite

The ability to obtain and maintain a U.S. government issued security clearance is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance

DoD Clearance:
Secret

Active and existing security clearance required after day 1

At RTX, the world largest aerospace and defense company, 185,000 great minds are united by purpose and inspired to make a difference solving the world’s most complex problems. With our three market leading businesses, world-class operations and investments in research and development, we offer capabilities and opportunity no one else can. Together, we push the boundaries of known science and find new ways to connect and protect our world.

The Radar Digital Products (RDP) Department at Raytheon is seeking an experienced Principal level Electrical Engineer to verify FPGA based designs for control and/or signal processing radar applications.

This position can be for the Tewksbury, MA location or the Marlborough, MA location.

• Own or contribute to the successful completion of FPGA-based designs, on time and on budget
• Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage using UVM
• Create complete documentation including verification plan and report
• Demonstrate self-motivation, with little supervision required
• Work cooperatively with systems, hardware, software engineers, and program management to ensure product success
• Support internal and external technical reviews

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 8 years of prior relevant experience
• Digital design verification
• Strong proficiency in System Verilog for both design and verification (interfaces, clocking blocks, assertions)
• Hands-on experience building UVM-based test benches from scratch, including env, agent, scoreboard, and coverage components
• Solid understanding of constrained-random verification and functional coverage methodology
• Familiarity with AXI, PCIe, Ethernet, DDR protocols.
• Experience with industry-standard simulators (e.g., Questa, VCS, Xcelium)
• Experience with regression management and debug of complex, intermittent failures
• Ability to develop and maintain verification plans tied to design specifications and coverage closure criteria
• Experience with version control systems (e.g., Git, Clear Case, SVN) in a team-based development environment

• Proficiency with Git. Branching strategies, pull requests, and collaborative workflows
• Experience with UVMF (UVM Framework) for structured, reusable testbench development
• Familiarity with Vivado and Quartus FPGA simulation flows
• Experience with scripting languages (Python, Tcl, Perl) for test automation and tooling
• Experience designing FPGAs using VHDL
• Familiarity with SLURM workload manager for job scheduling and compute cluster resource management
• Prior experience mentoring junior verification engineers
• Existing DoD security clearance

Our values drive our actions, behaviors, and performance with a vision for a safer, more connected world. At RTX we value:
Safety, Trust, Respect, Accountability, Collaboration and Innovation.

This position is eligible for relocation.

Clearance Information:
This position requires a security clearance. DCSA Consolidated Adjudication Services (DCSA CAS), an agency of the Department of Defense, handles and adjudicates the security clearance process. More information about Security Clearances can be found on the US Department of State government website here: https://(Use the "Apply for this Job" box below)..htm

Raytheon Information -

As part of our commitment to maintaining a secure hiring process, candidates may be asked to attend select steps of the interview process in-person at one of our office locations, regardless of…