Senior ASIC Physical Design Engineer

Johns Hopkins Applied Physics Laboratory (APL) seeks a Senior ASIC Physical Design Engineer to lead RTL-to-GDSII implementation for cutting-edge national security, space, and health missions. You will own floor planning, place-and-route, timing closure, and signoff for advanced-node ASICs and SoCs, collaborating with RTL, verification, and architecture teams. You'll guide EDA flow development, drive power and reliability optimization, and mentor junior engineers, all within APL's mission-driven, collaborative, and research-focused culture that supports innovation, advanced study, and career growth.

Responsibilities

• Lead end-to-end ASIC/So
• C physical design from RTL handoff through GDSII tapeout
• Develop and execute floor plans, clock trees, and power plans for complex digital designs
• Perform place-and-route, static timing analysis, and closure across multiple corners and modes
• Conduct power, IR drop, EM, DRC, and LVS signoff, coordinating with foundry PDKs and rules
• Collaborate with RTL, verification, and architecture teams to optimize performance, area, and power
• Enhance and automate EDA flows, scripts, and methodologies for physical implementation
• Mentor junior engineers and contribute technical leadership to multi-disciplinary project teams

Required Skills

• ASIC physical design
• So
• C floor planning
• Place-and-route (P&R)
• Static timing analysis (STA)
• Power, IR drop and EM analysis
• DFT-aware physical implementation
• Physical verification (DRC/LVS)
• Scripting (TCL/Perl/Python)
• RTL-to-GDSII flow tools (e.g., Synopsys, Cadence)
• Version control and CI flows