DDR PHY AMS Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers to PCs, gaming, and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover that our culture is the real differentiator.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

The candidate will be a Member of the Memory I/O design team supporting the definition, specification, system simulation and implementation of future LPDDR IPs. The focus of the activity will be centered around the circuit architecture and design of critical high‑speed analog and digital blocks, definition of algorithms for calibration, equalization and development of abstracted models for link performance simulations.

Will have strong experience building Memory PHY and high‑speed I/O with a track record of multiple successful tape‑outs and productization. Must possess analytical thinking, an inventive spirit, solid understanding of risks and mitigation, strong communication skills, and an enthusiastic team‑first mentality.

• Contribute to the definition of circuit architecture and to the design implementation of various state‑of‑the‑art, low‑power blocks and area‑efficient circuits for LPDDR PHY.
• Design circuits for high‑speed I/O that include transmissio… (complete list)
• Work closely with other teams to port design to different nodes while improving the overall PPA from previous generation.
• Develop models for link‑level statistical performance simulation of the PHY and apply the same to the development and optimization of design.
• Document the micro‑architecture and algorithms, and guide Analog, Digital, Firmware and Verification teams on training and verification of the circuits.
• Work closely with various disciplines—especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification—to ensure optimal implementation of the overall PHY architecture and algorithms with full coverage.
• Participate and contribute to the definition of development flows that improve efficiency and quality of execution.
• Lead design liaison for post‑silicon characterization and productization/volume production efforts.

• A proven successful track record in circuit architecture and modeling for high‑speed I/O.
• A proven track record of leading junior engineers to deliver complex circuits.
• Solid, hands‑on knowledge of algorithms and equalization/calibration/clocking techniques for high‑speed circuit design.
• Solid knowledge of industry‑standard tools and best‑in‑class practices for PHY modeling, both in terms of abstracted models (e.g., Matlab/Simulink) as well as Verilog/AMS‑based.
• Good knowledge of I/O and system integration (signaling/equalization techniques, signal integrity, power integrity).
• Ability to dig into RTL or firmware code supporting the custom circuit implementation.

• Bachelor’s or master’s degree in Computer Engineering or Electrical Engineering.

Boxborough, MA (open to Santa Clara, CA)

This role is not eligible for visa sponsorship.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available.

This posting is for an existing vacancy.