ASIC Physical Design Engineer

We are hiring a Senior Physical Design Engineer to drive RTL-to-GDSII implementation for advanced-node ASIC/SoC designs (28nm and below). This is a hands‑on role requiring strong ownership of block or partition‑level implementation and the ability to deliver signoff‑clean designs under aggressive tape‑out schedules.

• Own end-to-end physical implementation from netlist to GDSII
• Perform floor planning, macro placement, power planning, placement, CTS, and routing
• Drive timing closure across setup/hold and signal integrity issues
• Perform Static Timing Analysis using Prime Time or Tempus
• Implement ECOs and support late-stage timing convergence
• Analyze and resolve congestion, IR drop, and EM issues
• Collaborate closely with RTL, synthesis, and full-chip teams
• Support tape‑out and deliver signoff‑quality designs
• Develop TCL/Python scripts to improve flow efficiency

• BS/MS in Electrical or Electronics Engineering
• 7+ years of ASIC Physical Design experience
• Strong hands‑on experience in advanced nodes: 5nm, 7nm, 10nm, 14nm, 16nm, or 28nm
• Deep understanding of floor planning, CTS, STA, and timing closure
• Experience with Synopsys tools (ICC2, Fusion Compiler, Prime Time, StarRC) or Cadence tools (Innovus, Tempus)
• Experience with low‑power methodologies and UPF
• Proven tape‑out experience

• Block Owner or Partition Owner experience
• Exposure to full‑chip integration
• Experience with high‑performance designs (1.5–2GHz+)
• Power signoff experience (IR/EM analysis)
• Networking or high‑speed interface ASIC background

If you are interested or know someone who would be a strong fit, please message me directly.