ASIC Physical Design Engineer

Meet the Team

Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross‑functional experts capable of solving the challenges of next‑generation optical interconnects, resulting in industry-leading, award-winning products.

As a Physical Design Engineer with Acacia, you will focus on the technical execution of high-performance ASIC designs. Working as an individual contributor, you will lead the RTL-to-GDSII implementation flow for advanced semiconductor nodes, ensuring that Acacia’s networking platforms meet rigorous power, performance, and area (PPA) targets. You will be responsible for the successful delivery of assigned blocks from specification through to tapeout.

• Implement end-to-end RTL-to-GDSII implementation for advanced nodes (sub‑7 nm to 2 nm).
• Perform hierarchical floor planning, place and route, and clock/power distribution.
• Conduct static timing analysis (STA) and drive timing closure for multi‑mode/multi‑corner designs.
• Lead the physical design of assigned blocks, ensuring quality and alignment to project timelines.
• Develop and maintain automated scripts to improve design flow efficiency and methodology.
• Collaborate with RTL and DFT teams to debug and resolve complex physical implementation issues.
• Implement test plans and participate in design reviews to ensure robust, high‑quality work.
• Implement ECO strategies and support sign‑off processes.
• Contribute to the refinement of design methodologies and best practices within the engineering team.
• Document functional specifications and track progress for assigned project landmarks.

• Bachelors degree in Engineering + 5 years of related experience, or Masters degree in Engineering + 3 years of related experience.
• Demonstrated experience in ASIC physical design and implementation.
• Experience working with hierarchical floor planning, clock and power distribution, global signal and I/O planning along with physical convergence, timing closure, and hierarchical design methodology.
• Prior experience with power integrity analysis and working on designs >100M gates in advanced nodes.

• Experience with scripting using languages such as TCL, Perl, Python.
• Place & Route experience using tools such as Cadence Innovus or Synopsys ICC
  2.
• Experience with formal equivalence check, timing closure, signal integrity, EMIR, physical verification DRC/LVS.
• Synthesis experience including Synopsys DC/FC.
• Formal Verification experience using tools such as Synopsys Formality or Cadence LEC.
• Experience with static timing analysis including tools such as Tempus.
• Experience with block‑level EMIR closure.
• Physical Verification experience including tools such as Synopsys ICV or Mentor Calibre.

The starting salary range posted for this position is $135,800 to $195,100 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation, equity, or benefits.

• U.S. employees are offered medical, dental, vision insurance, a 401(k) plan with matching contribution, paid parental leave, short and long‑term disability coverage, and basic life insurance.
• Employees may be eligible to receive grants of Cisco restricted stock units that vest following continued employment.
• Paid holidays: 10 paid holidays per year, plus 1 floating holiday for non‑exempt employees.
• Non‑exempt employees receive 16 days of paid vacation per year.
• Exempt employees have flexible vacation with no defined limit.
• Sick time: 80 hours provided on hire date and each January 1st thereafter.
• Additional paid time for emergency situations and optional volunteer days.