ASIC Core DFT Technical Lead - Scan, ATPG, Bist

ASIC Technical Lead

As an ASIC Technical Lead, you will sit at the forefront of networking hardware innovation, directly shaping Cisco's industry-defining Silicon One architecture. You will drive cutting-edge Design-for-Test (DFT) strategies, bridging the gap between front-end RTL, physical design, and post-silicon validation to ensure elite quality for some of the industry's most complex ASICs. In this role, your technical leadership and custom DFT solutions will directly fuel the next generation of best-of-breed routing and switching systems deployed across global enterprises, web-scale data centers, and service providers.

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

• Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
• Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and post silicon debug.
• Experience with ATPG and EDA tools like Test Max, Tetramax, Tessent tool sets, Prime Time
• Prior verification experience including, System Verilog Logic Equivalency checking and validating the Test-timing of the design
• Prior experience with Tcl and Python/Perl.

• Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification
• DFT CAD development – Test Architecture, Methodology and Infrastructure

At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

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