Fpga Engineer Ii

Location

US‑TX‑MCKINNEY‑513WD ~ 2501 W University Dr ~ WING D BLDG (Onsite, McKinney, TX)

U.S. citizenship required. Ability to obtain and maintain a U.S. government‑issued security clearance required. Security Clearance Type:
Secret. Clearance must be active from day one.

At Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat.

We are currently seeking an FPGA Engineer II to join our team. This is an onsite role located in McKinney, TX.

• Provide full lifecycle support of production‑quality FPGA designs for one or more major vendors and device families including AMD (Xilinx), Altera, and Microchip (Microsemi).
• Generate FPGA designs for gigabit serial interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing and processor interfaces.
• Assist with architecture development of FPGA‑based systems to determine parts, interfaces, and Concept of Operations (CONOPS).
• Design and code in VHDL for reliability and maintainability.
• Support design verification utilizing self‑checking techniques with directed and constrained random tests while tracking functional and code coverage.
• Understand and report execution status to the planned budget and schedule using an agile framework.
• Create complete documentation including requirements, verification plan, and user’s guides.
• Function as an individual contributor.
• Clearly present your work product to leadership.
• Engage in professional growth and development.

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 2 years of prior relevant experience.
• Experience to include one or more of the following:
• FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding).
• Experience with AMD (Xilinx), Altera and/or Microchip (Microsemi) devices and with tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
• Hands‑on experience with integration and debug of FPGA/ASIC in a lab environment.
• Experience with source code management, design reviews, and code release in a team development environment.

• One or more advanced degrees in Electrical Engineering or a related STEM major. A suitable degree may be counted as 2 years of work experience.
• FPGA/ASIC design experience in one or more of the following areas:
• Embedded systems design using ARM, Microblaze, or NIOS processors.
• Gigabit serial interfaces and multi‑gigabit transceivers (MGTs).
• Constrained random verification in UVM using System Verilog.
• Experience with High Level Synthesis (HLS).
• Experience with vector processors and/or GPUs.
• Experience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.
• Demonstrated ability to lead design efforts and/or small teams.

• Salary range: $68,900 – $131,100 USD.
• Benefits include medical, dental, vision, life insurance, short‑term and long‑term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays.
• Hired applicants may be eligible for annual short‑term and/or long‑term incentive compensation programs depending on the level of the position.
• Priority may be given for relocation based on candidate eligibility.

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status, or any other applicable state or federal protected class. RTX provides affirmative action in employment for qualified individuals with a disability and protected veterans in compliance with Section 503 of the Rehabilitation Act and the Vietnam Era Veterans’ Readjustment Assistance Act.