Senior Digital Mixed-Signal; DMS Verification Engineer

Job Description Summary

Join Broadcom, a global technology leader and Fortune 500 powerhouse at the forefront of semiconductor innovation and AI infrastructure. Within our specialized Mixed‑Signal ASIC division, we build the critical IP that drives next‑generation enterprise storage solutions. We are looking for a Senior DMS Verification Engineer to act as a localized methodology leader and key technical bridge for our worldwide engineering organization.

This unique opportunity allows a verification architect to drive quality initiatives, pioneer modern automation (including AI‑assisted workflows), and establish robust methodologies across our US and Asia design centers.

• Architect, develop, and maintain advanced UVM‑based test benches for the functional verification of complex mixed‑signal ASIC products.
• Champion verification quality by integrating new methodologies, such as System Verilog Assertions (SVA) and UVM/OVM, to reduce mixed‑signal validation bottlenecks.
• Act as the primary liaison between our local US digital design teams and our worldwide verification teams, translating complex specifications into seamless execution.
• Lead initiatives to explore and integrate modern automation and AI‑assisted verification workflows to accelerate testbench generation and debug efficiency.
• Own verification efforts at both the block and system levels for major tape‑out projects, driving functional and code coverage to closure.

• 5+ years of hands‑on experience in digital verification of mixed‑signal ASICs or SoCs.
• Deep expertise in coverage‑driven verification processes and frameworks (UVM/OVM).
• A strong understanding of event‑driven simulator‑based modeling techniques and how digital logic interacts with analog boundaries.
• Proven ability to coordinate technical problem‑solving across cross‑site and global teams.
• Excellent English communication skills to translate product definitions into executable plans.
• Bachelors in Electrical Engineering, Computer Engineering, or Computer Science and 8+ years of related experience, or Masters degree in Engineering and 6+ years of related experience.

• Mixed‑signal ASIC UVM / OVM experience preferred.
• Hands‑on experience with System Verilog Assertions (SVA) and behavioral modeling of analog circuits.
• Proficiency in scripting to automate verification workflows, manage regressions, and streamline simulation infrastructure.

The annual base salary range for this position is $108,000 – $172,800. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: medical, dental and vision plans; 401(k) participation including company matching;
Employee Stock Purchase Program (ESPP);
Employee Assistance Program (EAP); company paid holidays; paid sick leave and vacation time. The company follows all applicable laws for paid family leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.