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Hardware Engineer, AI Accelerator Module Design

Job in Menlo Park, San Mateo County, California, 94029, USA
Listing for: Meta
Full Time position
Listed on 2026-08-27
Job specializations:
  • Engineering
    Hardware Engineer, Electrical Engineering, Electronics Engineer, Test Engineer
Salary/Wage Range or Industry Benchmark: 140000 - 180000 USD Yearly USD 140000.00 180000.00 YEAR
Job Description & How to Apply Below

Meta is building the next generation of AI infrastructure, and the silicon that powers it is central to that mission. As a Hardware Engineer focused on accelerator design, you will contribute to the development of custom AI accelerators and high-performance compute hardware that underpin Meta's data center infrastructure  this role, you will work across digital design, power delivery, signal integrity, and board‑level electrical engineering to bring accelerator systems from concept to production, directly enabling the AI workloads that power Meta's products and services.

  • BS in Electrical Engineering, Computer Engineering, or a related technical discipline
  • 2+ years of experience in electrical or hardware engineering with a focus on high-performance compute, accelerator, or data center hardware design
  • 2+ years of experience with PCB schematic capture, layout review, and signal integrity analysis for high-speed digital interfaces (e.g., PCIe, DDR, HBM, or Ser Des-based links)
  • 2+ years of experience with power delivery network design and analysis, including decoupling strategy, voltage regulator selection, and power integrity simulation
  • Experience with hardware bring‑up, electrical characterization, and debugging using lab instrumentation such as oscilloscopes, network analyzers, and power analyzers
  • Exposure to hardware reliability and qualification standards relevant to data center infrastructure (e.g., JEDEC, IPC)
  • Experience using simulation tools such as SPICE, Hyper Lynx, or Ansys SIwave for signal and power integrity analysis
  • Experience with custom ASIC or GPU accelerator board design, including co-design with silicon teams on package and board‑level electrical interfaces
  • Familiarity with thermal-electrical co-design considerations for high‑TDP accelerator systems in rack‑scale data center deployments
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