Memory System Architect

Mesa, AZ 85210 — Onsite Full-time Memory Architecture

Numem is currently seeking an experienced, hands‑on Memory System Architect to play a pivotal role in shaping our next generation of MRAM‑based AI memory products. This position is central to defining and evolving the architecture of our AI Memory Engine, discrete MRAM products (reaching capacities of 1GB+), and embedded memory subsystems across advanced process nodes ranging from 12nm down to 5nm.

In this role, you will be expected to lead architectural innovation and provide technical guidance throughout the design implementation phase. Furthermore, you will collaborate closely with customers on specific applications to address and resolve critical memory bottlenecks within AI‑centric systems.

Define architecture for MRAM‑based systems and AI Memory Engine

Lead modeling and performance analysis across power, latency, bandwidth, endurance, and area

Engage directly with customers to resolve AI memory bottlenecks

• Define overall architecture for MRAM based systems including bus interfaces balancing protocol, bandwidth, power and product cost
• Lead modeling and performance analysis for power, latency, bandwidth, endurance, and area trade‑offset
• Create system solutions that enable adapting MRAM based products to be performed with multiple different interface standards (LPDDR, UCIE, XSPI etc.)
• Document and be responsible for all the architecture specifications related to roadmap IP's and products
• Support customer acquisition and enablement using models and documents
• Develop and deliver system‑level modeling and simulation environment for next‑generation AI memory solutions

• Education:
  
  BS/MS in Electrical Engineering or Computer Engineering.
• Experience:
  
  8+ years of experience in memory architecture and memory IO interfaces at advanced nodes.
• Architecture:
  Demonstrated proficiency in creating and driving architecture specifications.
• Systems & Drivers:
  Exposure to system Linux drivers for LPDDR, PCIe, and CXL.
• Technical Integration:
  Strong system‑level perspective, including interaction with compute cores and SoC interconnects.
• Lifecycle
  
  Experience:
  
  Prior experience bringing memory subsystems from concept through silicon validation.
• Subsystem Knowledge:
  Detailed knowledge of cache subsystems (caching policies, latency, bandwidth, and hierarchies) and memory subsystem design, including existing/emerging JEDEC standards.
• Optimization:
  Understanding of the roles of CPU, memory hierarchy, and accelerators in optimizing system‑level power and performance for complex workloads.
• Modeling:
  Proficiency in various levels of modeling (analytical, TLM, cycle accurate) and their respective tradeoffs.
• Soft Skills:
  
  Excellent communication skills and the ability to work cross‑functionally in a fast‑paced startup environment.

• Working knowledge of simulation frameworks such as QEMU, Gem5, DRAMPower, DRAMSim, or other open‑source simulators.
• Familiarity with memory and interface technologies including DRAM, HBM, NVMe, CXL, and PCIe.

$ – $ per year

Job Type: Full-time

• 401(k)
• Health insurance
• Paid time off
• Vision insurance