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Metrology OCD Library Team Section Manager

Job in Mesa, Maricopa County, Arizona, 85201, USA
Listing for: TSMC - Taiwan Semiconductor Manufacturing Company Limited
Full Time position
Listed on 2026-06-18
Job specializations:
  • Engineering
    Process Engineer, Manufacturing Engineer, Quality Engineering, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 USD Yearly USD 80000.00 100000.00 YEAR
Job Description & How to Apply Below
Position: Metrology OCD Library Team Section Manager #5665

Job Title

Metrology OCD Library Team Section Manager #5665

Statement about position/company

A job at TSMC Arizona offers an opportunity to work at the most advanced semiconductor fab in the United States. TSMC Arizona’s first fab will operate its leading‑edge semiconductor process technology (N4 process), starting production in the first half of 2025. The second fab will utilize its leading edge N3 and N2 process technology and be operational in 2028. The recently announced third fab will manufacture chips using 2nm or even more advanced process technology, with production starting by the end of the decade.

America’s leading technology companies are ready to rely on TSMC Arizona for the next generations of chips that will power the digital future.

As a Metrology OCD Library Team Section Manager, you will demonstrate a strong sense of reliability and enthusiasm and will possess an attitude that embodies our core values – Integrity, Commitment, Innovation, and Customer Trust. Multiple positions available.

Metrology OCD Library Team Section Manager - Brief Description

Develop and optimize OCD RCWA/ML library and film strategy model for inline/offline measurements during Fab ramping, mass production for NTO/Process CIP, including working with HQ/AZ metrology, Module teams, vendors, and relevant stakeholders. Analyze OCD/Film spectrum in 3D/2D structure as well as inline result for problem‑solving and process improvement, including working with full route process loop Integration owner, Module, vendors, and relevant stakeholders.

Responsibilities
  • Support N5/N4/N3 production issue analysis to assist the Integration/Module/Metrology team in identifying root causes and providing technical insights for problem‑solving.
  • Establish spectrum RMSE comparison system to monitor cross‑fab inline process flow issue and matching.
  • Examine process tool chamber matching results based on spectrum errors to ensure proper tool chamber release.
  • Vendor coordination, including working with various metrology vendors for library and recipe setup, maintaining library workstation/server, upgrading systems, and troubleshooting.
  • Bolster engineers’ training in metrology measurement theory and library algorithm to enhance engineer knowledge.
  • Collaborate with various modules and integration to discuss and resolve metrology measurement issues.
Education and Work Experience
  • Must have a Master’s degree or foreign equivalent in Electronics Engineering, Electrical Engineering, Mechanical Engineering, Material Science, Chemical Engineering, Automation Engineering or a related field, plus 5 years of experience in an engineering role.
  • Alternatively, company will accept a Bachelor’s degree or foreign equivalent in Electronics Engineering, Electrical Engineering, Mechanical Engineering, Material Science, Chemical Engineering, Automation Engineering or a related field and 7 years of progressive, post baccalaureate experience in an engineering role.
Technical Skills
  • Must have 5 years of experience with semiconductor manufacturing principles, practices, and techniques as they relate to equipment engineering and maintenance.
  • Must have 5 years of experience with 5nm technology or below in logic chip semiconductor industry.
  • Must have 3 years of experience overseeing junior engineers.
  • Must have 3 years of experience in at least 1 of the following: 6‑sigma process control; chemical quality improvement; and air/liquid purifier system.
  • Must have 5 years of experience in KLA Acushape/OLSA, Onto Nano Diffract/WVASE and Nova Mars software modeling, including library development.
  • Education or experience with designing DoE wafers and optimizing libraries for TEM or reference tool linearity.
Physical Requirements
  • Candidates must be willing and able to work on‑site at our Phoenix Arizona facility.
Standard Work Hours

40 hrs/week, Mon-Fri, 8:30 a.m.

- 5:30 p.m.

Benefits

We offer a comprehensive and competitive benefits program that includes medical, dental, and vision plans, income‑protection programs, a 401(k) retirement savings plan, paid time‑off programs, and paid holidays.

Work Location

5088 W. Innovation Circle, Phoenix, AZ 85083

Equity and Diversity Statement

TSMC is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic. Candidates must be able to perform the essential functions of the job with or without a reasonable accommodation.

If you need a reasonable accommodation as part of this application process, please contact  Requisition 5665

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