Senior Lead Memory Circuit Design Engineer; Mixed-Signal​/NVM

Senior Lead Memory Circuit Design Engineer (Mixed-Signal / NVM)

Mesa, AZ 85210 — Onsite Full-time Memory Circuit Design

We are seeking a Senior Lead Memory Circuit Design Engineer to take end-to-end ownership of a production-grade memory subsystem in an advanced mixed-signal SoC. This role drives architecture-to-tapeout execution across memory arrays, read/write circuitry, sensing, reference generation, and data path integration. The successful candidate will collaborate closely with Analog, Digital/RTL, Verification, and Layout teams and will mentor junior engineers to deliver schedule-driven milestones through multiple tapeouts.

Numem is a California- and Arizona-based company that transforms next-generation memory technologies to power AI applications at the edge and data center. Our solutions deliver ultra-low latency, low power, and optimized density to meet the performance demands of modern AI workloads. We specialize in advancing foundry-based MRAM technologies, enhanced through state-of-the-art innovations in design, sense, power efficiency, and performance optimization, enabling a broad range of applications across edge and data-center environments.

• Own full memory subsystem delivery from specification, architecture, circuit design, verification, and signoff to tapeout.
• Define and refine memory block requirements (performance, power, robustness, testability) aligned to full-chip specifications.
• Circuit verification planning: SPICE test benches, PVT/temperature sweeps, Monte Carlo, mismatch, and reliability checks.
• Review Chip level STA timing violations related to the memory.
• Implement margin measures.
• Waveform review and document the summary and findings.
• Partner with Layout on floorplan constraints, parasitic‑aware design, EM/IR, density/fill, antenna, and signoff closure.
• Coordinate cross‑functional reviews, manage risks, and mentor junior engineers to achieve development milestones.

• BSEE/MSEE/PhD (or equivalent experience) in Electrical Engineering or related field.
• 15+ years of memory circuit design experience including SRAM and non‑volatile memory technologies.
• Proven record of multiple successful tapeouts with block or subsystem ownership.
• Deep expertise in mixed‑signal design fundamentals and memory read/write design tradeoffs.
• Strong experience with sense amplifier design, reference generation, and variation-aware margin analysis.
• Strong understanding of array architecture, disturb mechanisms, and robustness techniques (generalized, not technology-specific).
• Experience with address decoders, timing/control sequencing, and datapath integration.
• Hands‑on proficiency with Cadence and Synopsys design flows and SPICE‑class simulation tools (Prime Sim/HSPICE/Spectre).
• Ability to lead cross‑functional execution and mentor engineers while maintaining quality and schedule.

• Experience with advanced non‑volatile and resistive memory architectures, including crosspoint‑style arrays.
• Prior work on MRAM and/or RRAM designs, silicon characterization, and post‑silicon debug is desirable.
• Experience with reliability signoff considerations (EM/IR, ESD, latch‑up, safe operating area) as they apply to memory macros.
• Tools & Methods — Simulation:
  Prime Sim/HSPICE/Spectre (or equivalent), waveform/debug, sweep automation.
• Tools & Methods — Design:
  Cadence Virtuoso / Custom Compiler; mixed‑signal schematic capture and integration workflows.
• Tools & Methods — Verification: scripting for regression, corner/Monte Carlo automation, and results reporting (Python/TCL/Shell).
• Tools & Methods —
  
  Collaboration:
  
  clear documentation (specs, verification plans, acceptance tests, signoff reports).

Memory subsystem meets product goals with documented margins across PVT/temperature and robust standby/read/write behavior. Clean signoff closure with traceable acceptance tests and tapeout‑ready deliverables. Effective coordination across analog/digital/layout/verification teams and strong mentoring of junior engineers. Predictable execution aligned to program milestones with risks identified early and mitigations implemented.