IP Design Verification Engineer

Responsibilities

• Develop and execute comprehensive mixed-signal IP verification plans to ensure designs meet specifications
• Create and maintain test benches and verification environments using advanced methodologies such as UVM and OVM
• Perform analog behavioral modeling to validate design functionality, timing, and power objectives
• Identify, replicate, and debug presilicon bugs, root cause issues, and drive corrective measures
• Analyze coverage metrics to ensure verification completeness and propose improvements where needed
• Collaborate across disciplines to refine verification strategies, optimize designs, and achieve project goals
• Document test plans, methodologies, and results, and lead technical reviews with cross-functional teams
• Maintain and enhance existing verification infrastructure and methodologies to support evolving design challenges

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
• 4 or more years of experience;
  Master's degree with 3 or more years of experience; or PhD with no experience
• +3 years of experience in System Verilog, Verilog, and advanced verification methodologies such as UVM and OVM
• Experience with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium/Jasper Gold, or Mentor Questa
• Analog behavioral modeling
• High-speed IO IP verification
• Low-power validation
• Strong debugging skills in both analog and digital domains
• PCIe and/or UCIe protocols
• Test planning, test environment development, and test content development