Senior FPGA Engineer

Pixels on Target is a company based in Sunrise, FL, dedicated to delivering cutting‑edge thermal optic products. Our team utilizes disruptive technologies to provide unparalleled overmatch capabilities to support those defending our freedom. We offer customized solutions tailored to meet specific mission requirements, whether through developing new systems or enhancing existing designs.

This is a full‑time, on‑site role for a Senior FPGA Design Engineer at Pixels on Target LLC. The Senior FPGA Design Engineer will be responsible for integrating camera sensors and displays, implementing and optimizing image processing and AI/ML algorithms, and developing graphical overlays for advanced thermal optic systems.

Key responsibilities include architecting, designing, and implementing FPGA‑based systems using System Verilog, developing simulation test benches, performing thorough verification, and driving timing closure. The engineer will optimize algorithms and hardware architectures for performance, area, latency, and power efficiency. This role requires close collaboration with hardware, software, and AI teams to accelerate the development of intelligent, mission‑critical systems.

• Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field

• Minimum of 7+ years of experience in HDL implementation targeting FPGA‑based systems
• Proven experience optimizing algorithms for FPGA implementation, including pipelining, parallelization, and resource optimization
• Strong experience driving timing closure in complex FPGA designs
• Experience implementing and accelerating AI/ML algorithms on FPGA platforms
• Proven experience with HDL (System Verilog, Verilog, or VHDL) and Python in a professional setting
• Extensive experience with various FPGA architectures, especially Lattice
• Proficiency in collaborating with cross‑functional teams to integrate hardware and software solutions
• Hands‑on experience with FPGA development, simulation, and verification
• Familiarity with version control systems such as Git

• Strong proficiency in HDL languages:
  System Verilog, Verilog, and VHDL
• Experience optimizing FPGA architectures for throughput, latency, and power efficiency
• Demonstrated expertise in timing analysis and timing closure techniques
• Experience with FPGA design tools:
  Xilinx Vivado, Intel Quartus, Lattice Diamond
• Simulation and verification tools:
  Model Sim, Questa Sim, Vivado Simulator
• Scripting languages:
  Python and Tcl for automation and tool scripting
• Experience with FPGA architectures:
  Lattice (ECP5, MachXO), Xilinx, Intel (Altera)
• Experience implementing image processing pipelines and AI/ML acceleration on FPGAs
• Experience with high‑speed interfaces and protocols: PCIe, DDR3/DDR4, Ethernet
• Hardware debugging and validation using logic analyzers, oscilloscopes, and ILA tools
• Familiarity with Git‑based version control workflows
• Basic knowledge of embedded systems and microcontrollers (e.g., ARM Cortex, RISC‑V)

• Strong analytical and problem‑solving skills, with the ability to debug, optimize, and close timing on complex FPGA systems
• Excellent written and verbal communication skills, with the ability to articulate complex technical concepts clearly
• Strong teamwork and collaboration skills, with a proven track record of working effectively in cross‑functional engineering teams