ASIC Intern – Digital​/Mixed-Signal Design & Custom Hardware

Ludwig Computing ASIC Intern – Digital/Mixed-Signal Design & Custom Hardware Mill Valley, CA
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Internship primarily focused on ASIC-level design, including RTL development, synthesis, and physical design readiness

Harnessing Randomness, Accelerating Compute;

Creating the Foundational Technology for the Future of Intelligent Compute

About us:

At Ludwig Computing, we are solving the energy efficiency problem of intelligent compute. Our novel co-designed approach is optimized to deliver radical improvements in energy efficiency and performance for various AI workloads. We are building a future where high performance computing is powered by leaner, smarter, and extremely efficient hardware and software platforms. Join us at the ground floor as we build the future of intelligent compute.

About the Role

We are looking for a technically exceptional and intellectually curious Hardware Design Engineer intern who is passionate about hardware acceleration and wants to work on cutting-edge compute platforms. You will work directly with the founding team to assist in implementing and validating core logics, processing algorithms, and other subsystems. This is a hands‑on, research‑meets‑build role in developing custom blocks for advanced computational workloads.

This internship is primarily focused on ASIC-level design
, including RTL development, synthesis, and physical design readiness, with opportunities to explore FPGA-based prototyping and system‑level integration as part of our broader hardware development process.

Responsibilities

• Contribute to RTL‑level design and microarchitecture development in Verilog or System Verilog
• Perform functional simulation, debugging, and testbench development
• Support synthesis, static timing analysis, and LINTing/CDC checks
• Collaborate on design partitioning and integration with system‑level blocks
• Explore PPA tradeoffs (power, performance, area) for candidate logic blocks
• Work with physical design constraints, floor planning, and placement inputs when needed

Requirements

• Strong understanding of digital design fundamentals
  , including finite state machines, pipelining, and timing closure
• Experience writing RTL in Verilog or System Verilog
• Familiarity with ASIC design tools and flows (e.g., Synopsys Design Compiler, Cadence Genus, or open‑source equivalents)
• Understanding of synthesis and logic optimization concepts
• Ability to work with waveform viewers, simulation tools, and debug workflows
• Currently pursuing a degree in engineering (preferably Electrical Engineering, Computer Science)
• Experience with OpenCL or HLS‑based design targeting FPGA
• Exposure to numerical computing
  , inference workloads
  , or custom arithmetic units
• Familiarity with hardware/software co‑design and system‑level integration
• Prior work with FPGA development boards
• Understanding of memory system tradeoffs
• Interest in or exposure to ASIC design concepts
  , such as synthesis, floor planning, or RTL‑to‑GDS tool chains
• Familiarity with analog or mixed‑signal concepts where digital logic interacts with real‑world signals (e.g., comparators, sense amplifiers, DACs)
• Currently PhD/MS student in EE/CS

What You'll Gain

• Opportunity to work on next generation AI compute architectures
• First‑hand experience building ASIC logic blocks that map to advanced compute concepts
• Opportunity to explore digital and mixed‑signal system design and how analog behavior can interface with structured digital logic
• The opportunity to work on real logic that could be taped out
  , and understand what it means to go from RTL to GDS
• Hands‑on understanding of tradeoffs in high‑speed, energy‑efficient hardware design
• Mentorship from a team with expertise hardware‑software co‑design