New Grad ASIC Verification Engineer; SystemVerilog​/UVM

Position: New Grad ASIC Verification Engineer (SystemVerilog/UVM)
A leading semiconductor company located in Milpitas, United States, is seeking a Senior Engineer for ASIC Development Engineering. The successful candidate will focus on developing test plans, creating verification environments, and ensuring thorough IP release management. Responsibilities include debugging, running regressions, creating documentation, and collaborating within cross-functional teams. Required qualifications include a degree in Electrical Engineering and proficiency in System Verilog or Verilog.

Candidates must have strong problem-solving and communication skills.
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