Verification CAD Engineer

• Job Type (exemption status):
  Exempt position - Please see related compensation & benefits details below
• Business Function: ASIC Development Engineering
• Location (Secondary):
  Longmont Office--_USCO
  02

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.

Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.

Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

Job Description

We are seeking a self-directed Verification Methodology Engineer to design, build, and optimize the infrastructure that enables our global ASIC team to execute at high velocity. In this role, you will evaluate, integrate, and deploy advanced third‑party verification tools and infrastructure solutions while defining robust methodologies across the entire development lifecycle. Beyond architectural ownership, you will serve as a critical technical resource for the broader ASIC team, proactively identifying and resolving workflow bottlenecks, debug challenges, compute resource constraints, and license limitations.

Role Overview

You will contribute to Sandisk verification architecture and the verification productivity suite by scaling new verification solutions into the global team using agents, skills and other advanced techniques. You will be responsible for the creative engineering required to make the global team more productive. Rather than executing a predefined script, you will identify inefficiencies then architect a framework to support solutions.

Your goal is to build a portable, scalable environment where tools and infrastructure handle the complexity.

Essential Duties & Responsibilities

• Methodology Innovation: Deploy scalable & portable methodologies that function across different environments scaling from IP to SOC to enable "write once, run anywhere" capability.
• Cross-Functional Support: Provide expert-level support for ASIC Design and Verification teams. Provide the automation and workflows necessary for high-speed debug and data analysis.
• Automation & Tooling: Build robust Python-based frameworks for automated testbench generation, regression management, and intelligent failure triage.
• Infrastructure Architecting: Design, develop, and maintain CAD infrastructure for verification. Enable seamless handoffs between IP & SOC verification teams. Use advanced techniques like formal verification paired with AI to shift left verification development.

Required:

• Education: B.S./M.S. in Electrical Engineering, Computer Engineering, or Computer Science.
• ASIC DNA: 7+ years of Design Verification experience with a deep understanding of chip-level functional model building.
• HVL Mastery: Expert-level knowledge of System Verilog and UVM, including assertion-based (SVA) and coverage-driven (CDV) methodologies.
• Automation Powerhouse: Advanced proficiency in Python and Shell scripting. Experience with Perl is a plus.
• Modern Dev Stack: Comfortable using AI-assisted development tools to increase personal and team velocity.
• Engine Versatility: Strong understanding of the differences between Behavioral and Structural models, with experience porting environments across simulation and emulation platforms.
• Tools & Debug: Familiarity with Cadence ASIC verification tools (Xcelium, Sim…