DMTS Digital Design Engineer​/Chip Lead

Job Summary

Micron Technology’s Interface Pathfinding team operates at the leading edge of memory and storage solutions. As a Digital Design Engineer / Chip Lead you will anchor a senior team spanning analog design, layout, silicon characterization, physical design, and verification. In this full‑ownership role you define chip architecture, author and maintain RTL for all soft IP, own timing constraints, drive synthesis, and produce design documentation.

• Chip Architecture & Integration
  :
  Define top‑level architecture, partition responsibilities across hard and soft IP blocks, and integrate hard macros with third‑party soft IP.
• RTL Design
  :
  Author, review and maintain synthesizable RTL (System Verilog) for all soft IP control blocks, CSR/register file, clocking control logic, and top‑level integration.
• Timing Closure Leadership
  :
  Develop chip‑level timing constraints, define CDC strategy, provide timing budgets per block.
• Synthesis
  :
  Drive logic synthesis (DC/Genus) and guide optimization for PPA targets.
• IP Management
  :
  Define interfaces between PHY hard macro, third‑party soft IP, and internally designed blocks; manage IP integration agreements and vendor coordination.
• Tape‑Out Ownership
  :
  Own the tape‑out checklist sign‑off process and coordinate across Physical Design, Verification, and analog teams for clean handoff.
• Design Documentation
  :
  Author architecture specifications, block‑level design specifications, and interface control documents that serve as the authoritative reference.
• Follow‑On Roadmap
  :
  Capture design decisions, lessons learned, and architectural rationale to accelerate follow‑on chip development.

• Basic Qualifications
  • BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years ASIC/digital design experience with at least one prior tape‑out in a chip lead, design lead, or senior designer role.
  • Expert‑level proficiency in System Verilog RTL design and coding best practices.
  • Strong experience with logic synthesis tools (Synopsys Design Compiler or Cadence Genus) and static timing analysis (Prime Time or Tempus).
  • Proficiency with industry‑standard RTL simulation and debug tools (VCS, Xcelium, or equivalent; Verdi or DVE for waveform debug).
  • Solid understanding of CDC analysis methodologies and tools (Spy Glass, Jasper Gold CDC, or equivalent).
  • Demonstrated experience integrating hard and soft IP blocks in a mixed‑signal or PHY‑adjacent chip environment.
  • Ability to serve as a technical lead on a small team, making decisions with incomplete information and owning outcomes.
  • Strong written communication skills (specification writing).
• Preferred Qualifications
  • Experience with high‑speed PHY architectures (Ser Des, DDR, or equivalent analog I/O structures).
  • Familiarity with I2C management bus architecture, eye‑monitor control logic, or PRBS‑based error counting implementations.
  • Experience with DFT strategy definition including scan insertion, ATPG planning, and boundary‑scan for high‑speed I/O.
  • Familiarity with OTP/fuse‑based trim and calibration architectures for PHY analog parameters.
  • Prior experience in a small team or startup‑like environment where role boundaries are defined by need.

Salary Range
: $206,000 - $410,000 per year (base). Additional compensation may include benefits, bonuses, and equity.

EEO Statement
:
Micron is proud to be an equal‑opportunity workplace and an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.