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Senior ASIC Verification Engineer - SystemVerilog/UVM Expert
Job in
California, Moniteau County, Missouri, 65018, USA
Listed on 2026-02-15
Listing for:
Technical-Link N. America
Full Time
position Listed on 2026-02-15
Job specializations:
-
Engineering
Systems Engineer, Test Engineer
Job Description & How to Apply Below
A leading technology company in California seeks a highly experienced Verification Engineer to architect and develop verification environments and testbench components. Candidates should have a strong background in ASIC design verification, with a minimum of 12 years industry experience and proficiency in System Verilog and UVM. Successful candidates will demonstrate problem-solving skills and the ability to work independently as well as part of a team, bringing passion to challenging tasks.
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Position Requirements
10+ Years
work experience
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