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Principal Analog Design Engineer Speed SerDes Lead

Job in California, Moniteau County, Missouri, 65018, USA
Listing for: Dormont Manufacturing Co
Full Time position
Listed on 2026-05-29
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Electrical Engineering, Hardware Engineer
Job Description & How to Apply Below
Position: Principal Analog Design Engineer — High-Speed SerDes Lead
Location: California

Job Details:Job Description:

We are seeking a highly experienced and motivated Principal Analog Design Engineer to lead the design and validation of cutting-edge analog circuits for high-speed (112G and 224G) Ser Des applications. In this role, you will be a key technical driver in the definition, execution, and validation of complex analog and mixed-signal designs.

This role involves providing technical direction and mentorship to layout and less experienced analog design engineers, fostering a collaborative and knowledge-sharing culture. You will engage closely with cross-functional teams, including systems, digital design, and test engineering, to ensure robust design implementation and validation.

Strong problem-solving skills, analytical thinking, and a commitment to execution excellence are essential. As a principal-level engineer, you will be expected to demonstrate a proven track record of delivering high-quality results in advanced FinFET CMOS technology within high-speed Ser Des design environments. Excellent documentation and presentation skills are also required to clearly communicate complex design concepts and results.

The ideal candidate is self-driven, detail-oriented, and thrives in a fast-paced environment. You will actively participate in technical discussions across multiple disciplines, including analog/mixed-signal design, post-silicon validation, and system-level collaboration.

Desired traits:

• Excellent communication, documentation, and presentation skills.

• Strong problem-solving attitude and ability to deliver under tight schedules in a collaborative environment.

• Demonstrated leadership in cross-functional technical discussions and decision-making.

• Team player with a collaborative mindset, willingness to share knowledge, and a hands-on approach to problem-solving

Qualifications:

_ Minimum Qualifications _

Master’s degree in Electrical Engineering, Electronics Engineering, or related field.

• 8+ years of experience in analog/mixed-signal circuit design for high-speed Ser Des applications.
• Proven expertise in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, or Transmitter (TX) design.

• Strong understanding of high-speed communication standards such as PCIe (Gen5/Gen6) and Ethernet (100G/400G/800G).

• Solid foundational knowledge of analog design principles-noise, jitter, matching, stability, and linearity.

Hands-on experience with advanced FinFET CMOS process technologies (7nm or below).

• Proficiency in analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.

• Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits.

_ Preferred Qualifications _

Ph.D. in Electrical Engineering, Electronics Engineering, or related field.

• 10+ years of experience in analog design for high-speed Ser Des (56G/112G/224G) applications.

• Deep expertise in transmitter and receiver architecture, CDR loops, equalization techniques, and advanced ADC architectures.

• Familiarity with next-generation standards such as PCIe 6.0+, 800G/1.6T Ethernet, JESD, and other Ser Des protocols.

Hands-on experience in behavioral modeling (Verilog-A), MATLAB-based analysis, and automation scripting (Python/Tcl/Perl).

• Strong understanding of signal integrity, channel modeling, and system-level link performance.

• Proven ability to mentor junior engineers, guide layout implementation, and drive design reviews..

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary

Location:

US, California, Santa Clara

Additional Locations:

US, Arizona, Phoenix, US, Oregon, Hillsboro

Business group:

The Central Engineering Group (CEG) is Intel’s data-driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel’s product and foundry businesses.

Posting Statement:

All qualified applicants will receive…

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