Senior Digital VLSI Design Engineer

• Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, CDC and RDC sign‑off
• Responsible for defining and enforcing synchronization strategies across complex, multi‑clock domains
• Own the constraint creation process for synthesis, full‑chip CDC/RDC methodology
• Collaborate closely with Architecture and Chip Lead teams to review testability and DFT design early in the design cycle
• Mentor the broader design team on Synthesis, DFT, CDC/RDC best practices and drive automated flows

• BSEE required, MSEE/PHD preferred
• 8+ years of related experience
• Deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC)
• Mastery of structural and functional verification of crossings using industry‑standard tools (e.g., Spy Glass CDC/RDC, Spyglass Lint, Jasper Gold, or Meridian)
• Experience with high‑speed interfaces such as Ser Des, LPDDR5/6, DDR4/5 or HBM

Demonstrates deep expertise in Digital VLSI Design, focusing on Synthesis, DFT, CDC, and RDC methodologies. Proven ability to mentor teams and enforce best practices while collaborating with architecture and chip leads to ensure design testability.