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Senior ASIC DFT Engineer – Test & Silicon Innovation

Job in California, Moniteau County, Missouri, 65018, USA
Listing for: Jobtailor
Full Time position
Listed on 2026-08-02
Job specializations:
  • Engineering
    Test Engineer, Hardware Engineer, Electronics Engineer, Quality Engineering
Salary/Wage Range or Industry Benchmark: 130000 - 190000 USD Yearly USD 130000.00 190000.00 YEAR
Job Description & How to Apply Below
Location: California

Jobtailor is seeking an experienced Hardware DFT Engineer to lead test-data path development for ASIC devices, collaborating across design, verification, and manufacturing teams to ensure robust in-system test and diagnostics from concept to post‑silicon validation.

You will own DFT IP development, implement features for JTAG, boundary scan and memory BIST, validate with ATPG tools, work with gate-level simulation (VCS) and ATE patterns (P1687), and mentor peers while driving technical

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Position Requirements
10+ Years work experience
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