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Senior SoC Architect, RAS

Job in California, Moniteau County, Missouri, 65018, USA
Listing for: Jobtailor
Full Time position
Listed on 2026-09-05
Job specializations:
  • Engineering
    Test Engineer, Systems Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 140000 - 210000 USD Yearly USD 140000.00 210000.00 YEAR
Job Description & How to Apply Below
Location: California

  • Define and drive SoC-level RAS hardware architecture across CPUs, interconnects, memory systems, IOs, safety islands, firmware interfaces, and platform-level components
  • Own RAS features from concept through architecture specification, micro-architecture alignment, RTL implementation support, design verification, silicon validation, debug, and production readiness
  • Develop architectural requirements for fault detection, correction, containment, isolation, telemetry, error reporting, recovery, graceful degradation, serviceability, and diagnostic observability
  • Collaborate with design, verification, validation, firmware, software, and platform teams
  • Analyze interactions between RAS mechanisms and performance, power, reset flows, clocks, memory hierarchy, interconnect behavior, firmware-visible controls, and platform software
  • Create hardware specifications, architectural requirements, error-handling flows, design guidance, test plans, and architectural models using SystemC, C/C++, Python, or other relevant modeling environments
  • Plan and review verification and validation strategies, including error injection, recovery validation, coverage analysis, resiliency modeling, and cross-functional architecture reviews
  • Assist in failure analysis and silicon debug for lab, post-silicon, production, and field findings
  • Develop diagnostic screens and localization methods for latent, intermittent, and environment-sensitive failures
  • Apply RAS architecture principles to high-reliability, space-aware, and radiation-aware deployment environments
  • Follow industry standards and best practices related to RAS, functional safety, semiconductor reliability, debuggability, verification, validation, and silicon testing
  • Patent novel hardware architecture techniques improving system resiliency, observability, serviceability, and recovery

Requirements

  • MS or PhD degree in computer engineering, electrical engineering, or equivalent experience
  • At least 8+ years of SoC architecture, design, verification, reliability, silicon validation, or related hardware development experience
  • Strong understanding of Reliability, Availability, and Serviceability (RAS) in the SoC context
  • Experience defining and driving hardware architecture features through the full development lifecycle
  • Strong understanding of overall SoC architecture and ability to reason across micro-architecture, full-chip integration, firmware interfaces, software-visible behavior, platform flows, and customer use cases
  • Meaningful industry expertise in one or more SoC architecture areas such as RAS, safety, debug, clocks, resets, interconnects, memory controllers, IO technologies, platform integration, firmware-visible error handling, or diagnostic infrastructure
  • Hands-on experience with design verification, silicon validation, fault injection, coverage analysis, resiliency modeling, diagnostic development, or reliability validation methodology
  • Familiarity with radiation effects, space operation, or other high-reliability deployment environments is strongly valued
  • Excellent analytical, written, and verbal interpersonal skills
  • Ability to work effectively across architecture, design, verification, firmware, software, validation, and customer-facing teams

Core Competencies

Demonstrates expertise in SoC-level RAS hardware architecture, encompassing fault detection, correction, and recovery mechanisms. Proficient in collaborating across multidisciplinary teams to drive hardware architecture from concept through production readiness.

Highest-signal resume keywords

  • SoC Architecture
  • Reliability, Availability, and Serviceability (RAS)
  • Design Verification
  • Silicon Validation
  • Fault Injection

ATS Optimization Keywords

Hard Skills

  • SystemC
  • C/C++
  • Python
  • Architectural Requirements Development
  • Error Handling Flows
  • Resiliency Modeling
  • Diagnostic Development
  • Coverage Analysis
  • Silicon Debug
  • Failure Analysis

Soft Skills

  • Analytical Skills
  • Written Communication
  • Verbal Communication
  • Interpersonal Skills

Certifications & Qualifications

  • MS or PhD in Computer Engineering
  • Electrical Engineering

Industry Keywords

  • Functional Safety
  • Semiconductor Reliability
  • Debug
  • High-Reliability Deployment
  • Radiation Effects
  • Platform Integration
  • Firmware Interfaces
  • Memory Controllers
  • Interconnects
  • IO Technologies
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Position Requirements
10+ Years work experience
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