Sr TPM​/NPU

Contract to Hire:
Sr Staff Technical Program Manager, NPU
Mountain View, CA
Hybrid

We are Cariad, an automotive software development team with the Volkswagen Group. Our mission is to make the automotive experience safer, more sustainable, more comfortable, more digital, and more fun. We are building the leading tech stack for the automotive industry and creating a unified software platform for over 10 million vehicles per year. We’re looking for talented, digital minds to help us create code that moves the world and to shape the future of the car and everyone around it.

The Sr Staff Technical Program Manager, NPU within the NPU Hardware & Software organization is responsible for driving the successful execution of CARIAD’s Neural Processing Unit (NPU) development. The role orchestrates the chip development lifecycle and manages schedules, dependencies, and deliverables across internal teams and external design partners. This role owns end-to-end program execution for the NPU from architecture definition through tapeout, validation, and production readiness, in close partnership with hardware and software engineering leads to coordinate complex interdependencies and ensure delivery against functional, quality, and schedule targets.

• Responsible for achieving project objectives on time, on specification, on budget and on quality deliveries for the complete NPU development lifecycle
• Prepare, maintain and track formal project plans including schedules and deliverables across hardware design, verification, software, and system integration teams
• Communicate engineering requirements, specifications, project schedule, and budget constraints to cross-functional teams, including engineers, senior management and external partners
• Responsible for project reporting, risk management, and escalation processes
• Administer a formal design review process to validate each development phase completion and readiness for next phase
• Coordinate milestone tracking and dependency management across internal teams of 15+ engineers

• Serve as primary interface with foundry partners (TSMC, Global Foundries, etc.) for process technology and manufacturing readiness
• Manage relationships with design services partners for physical implementation, packaging, and test development
• Coordinate with IP vendors for processor cores, interface IP, and memory controllers integration
• Establish project schedules, technical requirements and delivery milestones with all external partners
• Facilitate joint development activities including design reviews, milestone assessments, and technical problem resolution

• Develop and maintain comprehensive risk registers with mitigation strategies and contingency plans
• Coordinate cross-functional risk assessment meetings and drive resolution of technical and schedule risks
• Establish quality gates and review processes aligned with automotive functional safety (ISO 26262) requirements
• Support silicon validation planning and coordinate with test teams for comprehensive NPU verification
• Drive continuous improvement initiatives to enhance development efficiency and quality

• Expert communicator across cultural and team boundaries
• Expertise in motivating teams and fostering a collaborative and productive environment
• Background in managing multiple and competing stakeholder interests; establishing trust, clear roles and responsibilities, and goodwill between partner engineering organizations
• Experience managing cross-functional and/or cross-team projects
• Stakeholder management expertise with ability to coordinate complex partner relationships
• Risk assessment and mitigation capabilities with proactive problem-solving approach
• Coordination expertise across technical teams and external partners
• Collaborate and work with partners for hardware development and tests
• Collaborate and work with multiple teams across geographies and time zones

• Extensive knowledge of semiconductor development lifecycle including architecture, RTL design, verification, physical implementation, and…