ASIC​/SOC Micro-Architect and RTL Design Engineer; Security Mountain View, CA

ASIC/SOC Micro-Architect and RTL Design Engineer (Security)

Mountain View, CA

MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity and other key technologies.

• Contribute to MatX’s silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, full-chip design
• Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design
• Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards various silicon milestones including design freeze and tapeout
• Work closely with the verification, DFT, and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results

• Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon
• Experience with System Verilog, Python, C/C++, Bluespec and similar scripting and programming languages for chip design and related flows
• Production-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management and related functionalities
• Experience with testing your designs and working closely with verification teams towards performance and coverage closure goals
• Hands-on experience with design synthesis, equivalence checking, design lint, clock-domain-crossing and related flows to take designs to high quality sign-off
• Experience on DFT and physical design concepts and methodologies to achieve high test coverage and best-in-class timing, power and area for designs working with experts in these areas to take designs to sign-off
• Familiarity with verification, emulation platforms and methodologies is a plus
• Hands-on experience with participation in silicon debug and bring-up is a plus
• This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday

• A huge plus if you have hands‑on experience with silicon and firmware implementations for hardware security features including Root of Trust (RoT), secure boot, lifecycle state machines, Key management, TRNG interfaces, Secure debug, secure firmware update paths, Access control, memory protection

The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.

• 0-5 years of experience - $120,000 - $200,000 + equity
• 5-10 years of experience - $120,000 -$300,000 + equity
• 10+ years experience - $120,000 - $400,000 + equity

• A Stake in our success – A cash/equity mix that fits your needs and option to do early exercise
• Health & Wellness – Company subsidized Health, Dental, Vision, and Life insurance;
  Pre-tax Health Savings Accounts with generous company contribution (even if you don’t)
• Time To Recharge – 4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year
• Support to Parents – Up to 12 weeks of paid parental leave, regardless of your path to parenthood
• Learning & Development – $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities
• Team Connection – Team Lunches, quarterly off-sites, and regular town halls
• Financial Wellbeing – 401K and/or Roth IRA, with 5% company…