Physical Design Engineer

Responsibilities

• Own floorplan-to-signoff physical design for one or more blocks of our AI accelerator silicon.
• Use and develop AI-assisted tool flows to accelerate physical design and signoff timelines.

• Exceptional abilities across the full physical design flow (synthesis, place & route, CTS, signoff)
• 8+ years of experience on very high performance designs at advanced technology nodes (7nm or better)
• Hands‑on with industry‑standard PD tools (Cadence Innovus, Synopsys Fusion Compiler, or equivalent) and signoff (Prime Time, Tempus, or equivalent)
• Demonstrated ability to work closely with architects, RTL designers, EDA vendors, and foundries to design and sign off complex chips
• (Optional) Multi‑die packaging (CoWoS, 2.5D / 3D), thermal / IR / EM signoff, signal integrity, or DFT‑aware physical design

Base salary: $200k – $350k USD per year, depending on experience and qualifications. Final offers depend on level, location, and skills relevant to the role.

Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO. Discussed in detail during the interview.

Density

AI sponsors qualified and exceptional candidates for employment‑based visas. Work authorization is required at start.

Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.

Density

AI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.