Physical Design Engineer

Acceler8 Talent is partnering with an early-stage, stealth-mode AI hardware startup to hire Physical Design Engineers to their team.

They are building an advanced AI-native compute platform spanning silicon and full-stack infrastructure for next-generation AI systems. They're seeking Physical Design Engineers to drive the implementation and optimization of cutting‑edge AI silicon. This is a highly technical role focused on physical implementation for a new class of compute architecture.

• Own floorplan-to-signoff physical design for one or more blocks within an AI accelerator SoC
• Develop and utilize AI‑assisted tooling flows to accelerate physical design and signoff timelines

• Strong expertise across the full physical design flow, including synthesis, place and route, clock tree synthesis, and signoff
• 8+ years of experience working on very high-performance designs at advanced process nodes (7nm or below)
• Hands‑on experience with industry‑standard physical design tools such as Cadence Innovus, Synopsys Fusion Compiler, or equivalent
• Experience with signoff tools such as Prime Time, Tempus, or equivalent
• Demonstrated ability to collaborate closely with architects, RTL designers, EDA vendors, and foundry teams to implement and sign off complex silicon designs

• Experience with advanced multi‑die packaging technologies such as CoWoS, 2.5D integration, or related heterogeneous packaging approaches

• Opportunity to help define physical implementation methodology for next‑generation AI compute platforms
• High‑impact technical ownership in a fast‑paced engineering environment
• Work on advanced silicon challenges spanning architecture, packaging, and AI infrastructure