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Principal Engineer, SI-PI

Job in Mountain View, Santa Clara County, California, 94039, USA
Listing for: Cariad, Inc.
Full Time position
Listed on 2026-06-02
Job specializations:
  • Engineering
    Systems Engineer, Electrical Engineering, Electronics Engineer
Job Description & How to Apply Below
We are CARIAD, an automotive software development team with the Volkswagen Group. Our mission is to make the automotive experience safer, more sustainable, more comfortable, more digital, and more fun. To achieve that we are building the leading tech stack for the automotive industry and creating a unified software platform for over 10 million new vehicles per year. We're looking for talented, digital minds like you to help us create code that moves the world.

Together with you, we'll build outstanding digital experiences and products for all Volkswagen Group brands that will transform mobility. Join us as we shape the future of the car and everyone around it.

Role Summary:

The Principal Engineer, SI/PI (Signal Integrity / Power Integrity) is the electrical performance expert for CARIADs high-speed automotive compute platforms (infotainment, ADAS ECUs). Scope spans compute modules and carrier boards, high-speed connectors/cables, and return-path/grounding considerations from concept through EVT/DVT/PVT. This role ensures clean high-speed signaling and robust power delivery across PCB, package, and system interconnects to prevent noise, jitter, data errors, EMI failures, and system instability.

The engineer influences schematic and layout decisions early, builds predictive models and simulations, and validates designs in the lab-partnering closely with SoC vendors, hardware/layout, EMC, and system validation teams to meet performance, EMC, and reliability targets.

Role Responsibilities:
  • Own channel budgets and SI sign-off reports per interface/program (margin targets, assumptions, and waiver rationale).
  • Analyze and optimize high-speed channels (PCIe, DDRx, Ethernet, MIPI/Ser Des) for loss, crosstalk, reflections, jitter, and margin.
  • Define routing/topology guidelines (impedance, spacing, length matching, reference planes) and review PCB layouts for compliance.
  • Partner with architecture and board teams to drive interface trade-offs and risk reductions early in design.
  • Signal Integrity Analysis & Design Enablement
  • Define PDN target-impedance specifications and PI sign-off reports per rail/domain (including transient/noise budgets).
  • Design and validate PDN across VRMs, planes, vias, and decoupling to meet target impedance and transient response goals.
  • Assess rail noise, droop/spike behavior, and coupling between power domains; recommend mitigation (placement, decaps, filters, sequencing).
  • Support power-up and load-step planning with system/SoC teams to ensure robust operation across use cases.
  • Maintain reusable SI/PI model library and simulation-to-measurement correlation reports; publish updated design rules/guard-bands.
  • Build and maintain SI/PI models (S-parameters, IBIS/IBIS-AMI, SPICE) and run what-if studies to predict risk before hardware build.
  • Use EM and circuit simulation tools (HFSS/SIwave/Sigrity/ADS or equivalents) to evaluate interconnects, packages, and planes.
  • Correlate simulation results to lab measurements and update models/rules to improve prediction accuracy.
  • Simulation, Modeling & Correlation
  • Produce lab measurement and correlation reports (eye/jitter/BER, PDN impedance/noise) and support pre-compliance EMI/EMC debug as needed.
  • Perform characterization using oscilloscopes, TDR, VNA, high-speed probing, and automated margining where applicable.
  • Debug electrical issues during bring-up and validation, including intermittent errors, eye closure, power noise-induced faults, and pre-compliance EMI/EMC issues.
  • Document root cause, corrective actions, and verification evidence to support release readiness.
  • Lab Validation, Bring-up & Debug
  • Own SI/PI sign-off checklist, waiver process, and 'golden' design-rule set; drive adoption across multiple boards/programs.
  • Lead design reviews and provide clear, actionable SI/PI sign-off criteria aligned with performance, EMC, and reliability targets.
  • Collaborate with EMC engineers to address emissions/susceptibility drivers tied to layout, grounding, shielding, and PDN behavior.
  • Mentor engineers and contribute to reusable design rules, checklists, and best-practice documentation across programs.
  • Cross-Functional Leadership & Standards
General Skills:
  • Technical leadership and systems-level thinking; able to influence design decisions across teams without direct authority.
  • Strong analytical and structured problem-solving skills; ability to diagnose complex electrical issues and drive closure.
  • Excellent communication skills (written, verbal, presentation) with ability to translate SI/PI findings into actionable design guidance.
  • Collaboration across global, cross-functional teams and suppliers; comfortable working across time zones.
  • High attention to detail and quality mindset; able to balance technical trade-offs across performance, cost, schedule, and manufacturability.
Required Specialized Skills:
  • Deep experience with high-speed interfaces (e.g., PCIe, DDRx, Automotive Ethernet, MIPI/Ser Des) and associated channel/receiver requirements.
  • Expertise in PCB stack-up, controlled-impedance routing,…
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