FPGA Verification Engineer

Technical Lead II - VLSI

United States, California, Mountain View

May 22, 2026

Born digital, UST transforms lives through the power of technology. We walk alongside our clients and partners, embedding innovation and agility into everything they do.

UST is a mission-driven group of 29,000+ practical problem solvers and creative thinkers in more than 30 countries.

Visit us at

We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify and debug issues, and contribute to overall product quality.

• Develop and execute comprehensive verification plans for FPGA designs.
• Create and maintain test benches using industry‑standard verification methodologies (e.g., UVM, System Verilog).
• Write and debug test cases to verify functionality, performance, and corner cases.
• Perform code coverage and functional coverage analysis.
• Identify and debug issues, working closely with design engineers to resolve them.
• Document verification results and provide clear and concise reports.
• Participate in design reviews and contribute to the overall verification strategy.
• Stay up-to-date with the latest verification methodologies and tools.

• Strong understanding of FPGA design principles and architectures.
• Proficiency in System Verilog and UVM verification methodology.
• Experience with industry‑standard verification tools (e.g., Questa Sim, Synopsys VCS).
• Knowledge of code coverage and functional coverage analysis.
• Excellent debugging and problem‑solving skills.
• Strong communication and collaboration skills.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of experience in FPGA verification.
• Experience with scripting languages (e.g., Python, Perl).
• Familiarity with hardware description languages (e.g., VHDL, Verilog).

• FPGA, RTL, UVM, System Verilog, VHDL, Verilog.

California

$101,000 – $152,000

Full‑time, regular employees accrue a minimum of 10 days of paid vacation per year, receive 6 days of paid sick leave each year (pro‑rated for new hires), 10 paid holidays, and are eligible for paid bereavement leave and jury duty. They are eligible to participate in the Company’s 401(k) Retirement Plan with employer matching. Employees and their dependents residing in the US are eligible for medical, dental, and vision insurance, as well as company‑paid employee benefits such as basic life insurance, accidental death and disability insurance, and short‑ and long‑term disability benefits.

Employees may purchase additional voluntary short‑term disability benefits, and participate in a Health Savings Account (HSA) and a Flexible Spending Account (FSA) for healthcare, dependent child care, and/or commuting expenses under IRS guidelines.

UST is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, status as a protected veteran, or any other applicable characteristics protected by law. UST will consider qualified applicants with arrest or conviction records in accordance with state and local laws and fair‑chance ordinances.