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Senior FPGA Verification Engineer; VLSI
Job in
Mountain View, Santa Clara County, California, 94039, USA
Listed on 2026-06-02
Listing for:
UST
Full Time
position Listed on 2026-06-02
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
UST is looking for a Technical Lead II - VLSI in Mountain View, California. As an FPGA Verification Engineer, you will verify complex designs and ensure their performance and reliability. The role requires strong proficiency in System Verilog and UVM methodology, along with at least 3 years of verified experience in FPGA verification.
The compensation range for this role is $101,000 to $152,000 annually, along with a comprehensive benefits package including medical insurance and a 401(k) plan.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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