Principal Engineer, RTL Design

Hi,

Hope you are doing well!

This is Aditya from Jconnect INC

Job Title: Principal Engineer, RTL Design

Employment Type: Contract
Location: Mountain View, CA (Hybrid)

Project Description
This role leads the development of complete hardware subsystems, shapes RTL design methodologies, influences architectural decisions, and ensures delivery of high performance, power efficient, and scalable silicon. Operating with a high degree of autonomy, the role partners closely with architecture, software, verification, and platform teams, and contribute to the technical direction of CARIAD's hardware platforms.

Responsibilities

RTL Design & Architecture (40%)

• Lead the design and implementation of complex RTL blocks, modules, and subsystems using Verilog/System Verilog for NPU architectures.
• Collaborate with system and microarchitecture architects to define and refine specifications, translating requirements into robust RTL solutions.
• Drive architectural and RTL decisions to optimize performance, power efficiency, and area (PPA) for AI workloads.
• Design and optimize compute engines, data paths, and memory hierarchies for high bandwidth, latency sensitive neural network processing.

Design Optimization & Performance Analysis (40%)

• Own timing analysis and timing closure strategies for complex designs, identifying and resolving critical paths.
• Apply advanced low power techniques, including clock gating and power aware design methodologies, to meet aggressive power targets.
• Lead area optimization efforts while preserving functional correctness and performance goals.
• Ensure testability by guiding and implementing design for test (DFT) strategies to support silicon validation and manufacturing readiness.

Integration, Validation & Technical Leadership (10%)

• Provide technical leadership during RTL integration, working closely with verification teams on simulation, emulation, and FPGA prototyping.
• Partner with software, hardware, and system teams to ensure seamless integration of the NPU into the broader vehicle compute platform.
• Review designs, mentor engineers, and set best practices for RTL quality, correctness, and maintainability.
• Author and review technical documentation, including design specifications, architecture reviews, and implementation guidelines.

Technology Direction & Cross Functional Influence (10%)

• Influence RTL and hardware development methodologies across programs, contributing to consistency and scalability of design practices.
• Evaluate emerging tools, technologies, and design approaches relevant to AI accelerators and automotive hardware platforms.
• Communicate complex technical concepts clearly to both technical and nontechnical stakeholders, supporting informed decision making.

Skills

Must have

• Expert communicator across global, cross-cultural, and cross-functional teams.
• Strong analytical, system level, and architectural thinking.
• Proven ability to lead technical initiatives without direct authority.
• High bar for design correctness, validation, and quality.
• Collaborative mindset across hardware, software, and verification organizations.
• Extensive experience in RTL design using Verilog/System Verilog for complex digital systems, preferably NPUs or AI accelerators.
• Proficiency with EDA tools for synthesis, simulation, and timing analysis (Synopsys, Cadence, Mentor).
• Strong understanding of computer architecture, microarchitecture, and hardware/software co-design.
• Experience with FPGA prototyping, emulation platforms (e.g., VCS, Palladium), and HW/SW co-verification.
• Scripting experience (Python, Perl) for automation and productivity.
• Deep knowledge of low power design and power optimization techniques.

Nice to have

• Knowledge of ADAS and automotive hardware requirements.
• Experience with AI/ML acceleration and neural network processing architectures.
• Background in high performance and parallel computing design.
• Familiarity with functional safety concepts (ISO 26262) and safety critical hardware design.
• Experience with advanced semiconductor process nodes and associated challenges.
• Exposure to GenAI assisted engineering tools and modern, AI augmented development workflows.
• Demonstrated track record of delivering complex RTL designs from concept through silicon production.

Please send me your updated resume ASAP with below details:

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Best Regards,

Aditya Srivastava
(IT Recruiter)

Jconnect Infotech Inc.
168 Barclay Center Ste. 347
Cherry Hill, NJ 08034
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[We are an E-Verify and Equal Employment Opportunity Employer with adherence to EEO policy]