Principal Engineer, Design Verification; NPU

Position: Principal Engineer, Design Verification (NPU)
Hi,

Hope you are doing well!

This is Parnika from Jconnect INC

Job Title: Principal Engineer, Design Verification (NPU)

Employment Type: Contract
Location: Mountain View, CA (Hybrid)

Project Description
The Principal Design Verification Engineer, within the NPU Hardware & Software organization, is intended for an individual with a broad background in design verification and complex digital system validation, with significant experience in AI accelerator verification and automotive safety standards.
This role drives verification excellence for a state-of-the-art Neural Processing Unit (NPU) by developing comprehensive test benches and validation methodologies to ensure functional correctness and performance. The role also leads development of verification infrastructure, including scalable regression frameworks and coverage-driven methodologies to deliver a safety-critical NPU meeting automotive industry requirements.

Responsibilities

Verification Planning & Strategy (40%)

• Develop verification plans and test plans for NPU functional blocks and system-level integration
• Define verification milestones, coverage goals, and success criteria
• Create verification strategies for AI workloads including convolution engines, matrix multiply units, and activation functions

Testbench Development & Implementation (40%)

• Design and implement System Verilog/UVM test benches for NPU verification
• Develop constrained random test generators for neural network inference pipelines
• Create reference models and checkers for AI workload validation
• Build verification environments for memory subsystems, DMA controllers, and system interconnects
• Implement functional and code coverage methodologies

System Integration & Performance Verification (20%)

• Verify AXI4/AHB protocol compliance and system-level interfaces
• Validate timing, throughput, and power consumption requirements
• Maintain regression test suites for CI
• Collaborate on hardware-software co-verification
• Support FPGA prototyping and emulation platforms
• Ensure compliance with ISO 26262 functional safety requirements

Skills

Must Have

• Expert communicator across global and cross-functional teams
• Strong analytical, debugging, and system-level problem-solving skills
• Ability to lead complex technical initiatives without direct authority
• Quality-driven mindset focused on correctness, robustness, and coverage
• Collaborative approach across hardware, software, verification, and safety teams
• Expert System Verilog and UVM-based verification
• Coverage-driven, constrained-random, and formal verification
• Verification automation using Python/Perl
• FPGA prototyping and emulation-based validation

Nice to Have

• Automotive functional safety (ISO 26262)
• Power-aware and low-power verification techniques
• GenAI-assisted verification workflows
• Verification of AI accelerators, NPUs, and complex digital subsystems
• AXI4/AHB protocol and memory subsystem verification

Please send me your updated resume ASAP with below details:

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Best Regards,

Parnika Shukla

Jconnect Infotech Inc.

168 Barclay Center Ste. 347

Cherry Hill, NJ 08034

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