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Senior Verification Engineer: UVM/SystemVerilog ASICs
Job in
Mountain View, Santa Clara County, California, 94039, USA
Listed on 2026-06-05
Listing for:
Towards AI, Inc.
Full Time
position Listed on 2026-06-05
Job specializations:
-
Engineering
Systems Engineer, Test Engineer
Job Description & How to Apply Below
A tech company in California is seeking an experienced engineer to develop and scale test benches using System Verilog and UVM methodologies. The role requires expertise in ASIC with a minimum of 8 years in the field and proficiency in scripting languages like Perl and Python. Responsibilities include regression activities and collaborating with a team to ensure verification closure. This position is integral to the startup environment, emphasizing customer satisfaction and effective progress reporting.
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Position Requirements
10+ Years
work experience
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