Design Verification Engineer

Acceler8 Talent is partnering with an early-stage, stealth-mode AI hardware startup to hire Design Verification Engineers.

They are building an advanced AI-native compute platform spanning silicon and full-stack infrastructure for next-generation AI systems. They're seeking Design Verification Engineers to define and build verification infrastructure for next-generation AI compute silicon. This is a highly hands-on role focused on building verification environments and methodology from the ground up for a new architecture.

• Own block-level RTL verification across an AI accelerator ASIC
• Build test benches, drive coverage closure, and leverage AI-assisted tooling flows to accelerate verification timelines

• Strong expertise in System Verilog, UVM, constrained-random verification, and coverage-driven methodologies
• 7+ years of experience verifying complex digital designs at the block or subsystem level
• Hands-on experience with industry-standard simulators such as VCS, Xcelium, Riviera, or equivalent
• Experience using waveform/debug tools such as Verdi, Sim Vision, or equivalent
• Demonstrated ability to debug RTL/testbench mismatches and drive functional coverage to target metrics

• Emulation platforms
• Processor or accelerator verification experience

• Opportunity to help define verification infrastructure and methodology for a new compute architecture
• High-impact technical ownership in a fast-moving engineering environment
• Work at the intersection of AI systems and advanced silicon development