Principal Engineer, RTL Design

Job Title

Expert communicator across global, cross-cultural, and cross-functional teams.

Strong analytical, system level, and architectural thinking.

Proven ability to lead technical initiatives without direct authority.

High bar for design correctness, validation, and quality.

Collaborative mindset across hardware, software, and verification organizations.

Extensive experience in RTL design using Verilog/System Verilog for complex digital systems, preferably NPUs or AI accelerators.

Proficiency with EDA tools for synthesis, simulation, and timing analysis (Synopsys, Cadence, Mentor).

Strong understanding of computer architecture, microarchitecture, and hardware/software co design.

Experience with FPGA prototyping, emulation platforms (e.g., VCS, Palladium), and HW/SW co-verification.

Scripting experience (Python, Perl) for automation and productivity.

Deep knowledge of low power design and power optimization techniques.

Knowledge of ADAS and automotive hardware requirements.

Experience with AI/ML acceleration and neural network processing architectures.

Background in high performance and parallel computing design.

Familiarity with functional safety concepts (ISO 26262) and safety critical hardware design.

Experience with advanced semiconductor process nodes and associated challenges.

Exposure to GenAI assisted engineering tools and modern, AI augmented development workflows.

Demonstrated track record of delivering complex RTL designs from concept through silicon production.